Parallel architecture of power-of-two multipliers for FPGAs.

Stefania Perri Fanny Spagnolo Fabio Frustaci Pasquale Corsonello

Published in: IET Circuits Devices Syst. (2020)

Keyphrases

parallel architecture
hardware implementation
parallel processing
systolic array
shared memory
field programmable gate array
power consumption
signal processing
parallel implementation
high level synthesis
parallel algorithm
parallel architectures
clock frequency
synthetic aperture sonar
distributed memory