Efficient implementation of signed multipliers on FPGAs.
Fanny SpagnoloPasquale CorsonelloFabio FrustaciStefania PerriPublished in: Comput. Electr. Eng. (2024)
Keyphrases
- efficient implementation
- hardware implementation
- field programmable gate array
- parallel architectures
- hardware software
- active set
- fpga technology
- embedded systems
- lagrangian relaxation
- feature extraction
- hardware and software
- map reduce
- hardware design
- structuring elements
- highly parallel
- least squares
- pairwise
- feature space