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Adaptive Cache Memories for SMT Processors.

Sonia LópezOscar GarnicaDavid H. AlbonesiSteven G. DropshoJuan LancharesJosé Ignacio Hidalgo
Published in: DSD (2010)
Keyphrases
  • embedded processors
  • multithreading
  • memory hierarchy
  • parallel processing
  • parallel algorithm
  • hit rate
  • query processing
  • data access
  • prefetching
  • parallel processors