Sonia López

Publication Activity (10 Years)

Years Active: 2003-2023
Publications (10 Years): 10

Top Topics

Computational Tools

High Level Synthesis

Heterogeneous Systems

Cognitive Architectures

Top Venues

Cogn. Syst. Res.

IPDPS Workshops

Publications

José-Antonio Cervantes, Sonia López, Jahaziel Molina, Francisco López, Mónica Fabiola Perales Tejeda, Jesus Carlos Carmona-Frausto
CogniDron-EEG: A system based on a brain-computer interface and a drone for cognitive training. Cogn. Syst. Res. 78 (2023)
Adriana Mexicano, J. C. Carmona, Salvador Cervantes, Jose-Antonio Cervantes, Sonia López, R. Rodríguez
A Modified Version of K-Means Algorithm. 3PGCIC (2021)
Sonia López, José-Antonio Cervantes, Salvador Cervantes, Jahaziel Molina, Francisco Cervantes
The plausibility of using unmanned aerial vehicles as a serious game for dealing with attention deficit-hyperactivity disorder. Cogn. Syst. Res. 59 (2020)
José-Antonio Cervantes, Sonia López, Luis-Felipe Rodríguez, Salvador Cervantes, Francisco Cervantes, Félix Ramos
Artificial Moral Agents: A Survey of the Current Status. Sci. Eng. Ethics 26 (2) (2020)
Salvador Cervantes, Sonia López, José-Antonio Cervantes
Toward ethical cognitive architectures for the development of artificial moral agents. Cogn. Syst. Res. 64 (2020)
Sonia López, José-Antonio Cervantes, Salvador Cervantes, Jahaziel Molina, Francisco Cervantes
Brain-Computer Interfaces for Controlling Unmanned Aerial Vehicles: Computational Tools for Cognitive Training. BICA (2019)
Sonia López, Stavan Satish Karia
Alternative Processor Within Threshold: Flexible Scheduling on Heterogeneous Systems. IPDPS Workshops (2017)
José-Antonio Cervantes, Jonathan-Hernando Rosales, Sonia López, Félix Ramos, Marco A. Ramos
Integrating a cognitive computational model of planning and decision-making considering affective information. Cogn. Syst. Res. 44 (2017)
Tejaswini Ananthanarayana, Sonia López, Marcin Lukowiak
Power Analysis of HLS-Designed Customized Instruction Set Architectures. IPDPS Workshops (2017)
José-Antonio Cervantes, Luis-Felipe Rodríguez, Sonia López, Félix Ramos, Francisco Robles
Autonomous Agents and Ethical Decision-Making. Cogn. Comput. 8 (2) (2016)
Sam Skalicky, Tejaswini Ananthanarayana, Sonia López, Marcin Lukowiak
Designing customized ISA processors using high level synthesis. ReConFig (2015)
Sam Skalicky, Andrew G. Schmidt, Sonia López, Matthew French
A unified hardware/software MPSoC system construction and run-time framework. DATE (2015)
Sam Skalicky, Sonia López, Marcin Lukowiak, Andrew G. Schmidt
A Parallelizing Matlab Compiler Framework and Run Time for Heterogeneous Systems. HPCC/CSS/ICESS (2015)
Sonia López, Jose-Antonio Cervantes, Félix Ramos, Yingxu Wang
A cognitive model of motor planning for virtual creatures. ICCI*CC (2015)
Sam Skalicky, Sonia López, Marcin Lukowiak
Performance modeling of pipelined linear algebra architectures on FPGAs. Comput. Electr. Eng. 40 (4) (2014)
Sam Skalicky, Tyler Kwolek, Sonia López, Marcin Lukowiak
Enabling FPGA support in Matlab based heterogeneous systems. ReConFig (2014)
Sam Skalicky, Sonia López, Marcin Lukowiak, Christopher A. Wood
Mission control: A performance metric and analysis of control logic for pipelined architectures on FPGAs. ReConFig (2014)
Jose-Antonio Cervantes, Luis-Felipe Rodríguez, Sonia López, Félix Ramos
A biologically inspired computational model of Moral Decision Making for autonomous agents. ICCI*CC (2013)
Sam Skalicky, Sonia López, Marcin Lukowiak, James Letendre, Matthew Ryan
Performance Modeling of Pipelined Linear Algebra Architectures on FPGAs. ARC (2013)
Sam Skalicky, Sonia López, Marcin Lukowiak, James Letendre, David Gasser
Linear algebra computations in heterogeneous systems. ASAP (2013)
Jose-Antonio Cervantes, Luis-Felipe Rodríguez, Sonia López, Félix Ramos, Francisco Robles
Cognitive Process of Moral Decision-Making for Autonomous Agents. Int. J. Softw. Sci. Comput. Intell. 5 (4) (2013)
Sam Skalicky, Sonia López, Marcin Lukowiak
Distributed execution of transmural electrophysiological imaging with CPU, GPU, and FPGA. ReConFig (2013)
Sonia López, Oscar Garnica, David H. Albonesi, Steven G. Dropsho, Juan Lanchares, José Ignacio Hidalgo
A phase adaptive cache hierarchy for SMT processors. Microprocess. Microsystems 35 (8) (2011)
Sonia López, Oscar Garnica, David H. Albonesi, Steven G. Dropsho, Juan Lanchares, José Ignacio Hidalgo
Adaptive Cache Memories for SMT Processors. DSD (2010)
Josefa Díaz, José Ignacio Hidalgo, Francisco Fernández, Oscar Garnica, Sonia López
Improving SMT performance: an application of genetic algorithms to configure resizable caches. GECCO (Companion) (2009)
Sonia López, Steve Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares
Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches. HiPEAC (2007)
Guadalupe Miñana, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar, Oscar Garnica, Sonia López
Reducing power of functional units in high-performance processors by checking instruction codes and resizing adders. IET Comput. Digit. Tech. 1 (2) (2007)
Sonia López, Steven G. Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares
Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors. PACT (2007)
Guadalupe Miñana, José Ignacio Hidalgo, Oscar Garnica, Juan Lanchares, José Manuel Colmenar, Sonia López
A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors. PATMOS (2006)
José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López
Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart. DSD (2006)
José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López
Sim-async: An Architectural Simulator for Asynchronous Processor Modeling Using Distribution Functions. Euro-Par (2006)
José Manuel Colmenar, Oscar Garnica, Sonia López, José Ignacio Hidalgo, Juan Lanchares, Román Hermida
Empirical Characterization of the Latency of Long Asynchronous Pipelines with Data-Dependent Module Delays. PDP (2004)
Sonia López, Oscar Garnica, José Manuel Colmenar
Enhancing GALS Processor Performance Using Data Classification Based on Data Latency. PATMOS (2004)
Sonia López, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, Román Hermida
Power-Consumption RRRRreduction in Asynchronous Circuits Using Delay Path Unequalization. PATMOS (2003)