Tejaswini Ananthanarayana

Publication Activity (10 Years)

Years Active: 2015-2023
Publications (10 Years): 11

Top Topics

Instruction Set Architecture

Top Venues

Food and Agricultural Imaging Systems

Publications

Tejaswini Ananthanarayana, Lipisha Chaudhary, Ifeoma Nwogu
SignNet: Single Channel Sign Generation using Metric Embedded Learning. FG (2023)
Lipisha Chaudhary, Tejaswini Ananthanarayana, Enjamamul Hoq, Ifeoma Nwogu
SignNet II: A Transformer-Based Two-Way Sign Language Translation Model. IEEE Trans. Pattern Anal. Mach. Intell. 45 (11) (2023)
Tejaswini Ananthanarayana, Lipisha Chaudhary, Ifeoma Nwogu
SignNet: Single Channel Sign Generation using Metric Embedded Learning. CoRR (2022)
Tejaswini Ananthanarayana, Lipisha Chaudhary, Ifeoma Nwogu
Effects of Feature Scaling and Fusion on Sign Language Translation. Interspeech (2021)
Tejaswini Ananthanarayana
A Computational Approach to Sign Language Understanding. AAAI (2021)
Tejaswini Ananthanarayana, Priyanshu Srivastava, Akash Chintha, Akhil Santha, Brian Landy, Joseph Panaro, Andre Webster, Nikunj R. Kotecha, Shagan Sah, Thomastine Sarchet, Raymond Ptucha, Ifeoma Nwogu
Deep Learning Methods for Sign Language Translation. ACM Trans. Access. Comput. 14 (4) (2021)
Tejaswini Ananthanarayana, Nikunj R. Kotecha, Priyanshu Srivastava, Lipisha Chaudhary, Nicholas Wilkins, Ifeoma Nwogu
Dynamic Cross-Feature Fusion for American Sign Language Translation. FG (2021)
Tejaswini Ananthanarayana, Raymond W. Ptucha, Sean C. Kelly
Deep Learning based Fruit Freshness Classification and Detection with CMOS Image sensors and Edge processors. Food and Agricultural Imaging Systems (2020)
Tiantian Yuan, Shagan Sah, Tejaswini Ananthanarayana, Chi Zhang, Aneesh Bhat, Sahaj Gandhi, Raymond W. Ptucha
Large Scale Sign Language Interpretation. FG (2019)
Tejaswini Ananthanarayana, Sonia López, Marcin Lukowiak
Power Analysis of HLS-Designed Customized Instruction Set Architectures. IPDPS Workshops (2017)
Sam Skalicky, Tejaswini Ananthanarayana, Sonia López, Marcin Lukowiak
Designing customized ISA processors using high level synthesis. ReConFig (2015)