Guadalupe Miñana

Publication Activity (10 Years)

Years Active: 2005-2024
Publications (10 Years): 1

Top Topics

Students Learning

Reinforcement Learning

Top Venues

Publications

Marcos Sánchez-Élez, Inmaculada Pardines, Pablo García, Guadalupe Miñana, Sara Román Navarro, Margarita Sánchez, José L. Risco-Martín
Enhancing Students' Learning Process Through Self-Generated Tests. CoRR (2024)
Victoria López, Matilde Santos Peñas, Guadalupe Miñana, Raquel Caro, Susanne Escobar-Torres Kraemmer, M. Sánchez Balmaseda, Guillermo Botella Juan
Memories in Complutense Campus. A Tribute to Prof. Dr. Da Ruan (2013)
Guadalupe Miñana, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar, Oscar Garnica, Sonia López
Reducing power of functional units in high-performance processors by checking instruction codes and resizing adders. IET Comput. Digit. Tech. 1 (2) (2007)
Guadalupe Miñana, José Ignacio Hidalgo, Oscar Garnica, Juan Lanchares, José Manuel Colmenar, Sonia López
A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors. PATMOS (2006)
José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López
Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart. DSD (2006)
Guadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar
A Power-Aware Technique for Functional Units in High-Performance Processors. DSD (2006)
José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López
Sim-async: An Architectural Simulator for Asynchronous Processor Modeling Using Distribution Functions. Euro-Par (2006)
Guadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar
Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width. PATMOS (2005)