Juan Lanchares

Publication Activity (10 Years)

Years Active: 1997-2024
Publications (10 Years): 19

Top Topics

Grammatical Evolution

Evolvable Hardware

Top Venues

GECCO (Companion)

Biomed. Signal Process. Control.

Publications

José L. Risco-Martín, J. Manuel Colmenar, José Ignacio Hidalgo, Juan Lanchares, Josefa Díaz
A methodology to automatically optimize dynamic memory managers applying grammatical evolution. CoRR (2024)
Juan Lanchares, Oscar Garnica, José L. Risco-Martín, José Ignacio Hidalgo, J. Manuel Colmenar, Alfredo Cuesta-Infante
Real Time Evolvable Hardware for Optimal Reconfiguration of Cusp-Like Pulse Shapers. CoRR (2024)
Jorge Cano, José Ignacio Hidalgo, Oscar Garnica, Juan Lanchares
Hardware design of a model generator based on grammars and cartesian genetic programming for blood glucose prediction. GECCO Companion (2023)
Josefa Díaz Álvarez, J. Manuel Colmenar, José L. Risco-Martín, Juan Lanchares, Oscar Garnica
Optimizing L1 cache for embedded systems through grammatical evolution. CoRR (2023)
Felix Tena, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo
A Critical Review of the state-of-the-art on Deep Neural Networks for Blood Glucose Prediction in Patients with Diabetes. CoRR (2021)
Felix Tena, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo
Ensemble Models of Cutting-Edge Deep Neural Networks for Blood Glucose Prediction in Patients with Diabetes. Sensors 21 (21) (2021)
Oscar Garnica, Juan Lanchares, J. Manuel Velasco, José Ignacio Hidalgo, Marta Botella
Noise spectral analysis and error estimation of continuous glucose monitors under real-life conditions of diabetes patients. Biomed. Signal Process. Control. 61 (2020)
Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo
Optimal Runtime Algorithm to Improve Fault Tolerance of Bus-Based Reconfigurable Designs. IEEE Trans. Very Large Scale Integr. Syst. 28 (4) (2020)
José Ignacio Hidalgo, Marta Botella, J. Manuel Velasco, Oscar Garnica, Carlos Cervigón, Remedios Martínez, Aranzazu Aramendi, Esther Maqueda, Juan Lanchares
Glucose forecasting combining Markov chain based enrichment of data, random grammatical evolution and Bagging. Appl. Soft Comput. 88 (2020)
José Ignacio Hidalgo, Ricardo Fernández, J. Manuel Colmenar, Oscar Garnica, Juan Lanchares, Gaspar González-Doncel
Determination of microscopic residual stresses using evolutionary algorithms. GECCO (Companion) (2019)
José Ignacio Hidalgo, Ricardo Fernández, Oscar Garnica, J. Manuel Colmenar, Juan Lanchares, Gaspar González-Doncel
Determination of microscopic residual stresses using diffraction methods, EBSD maps, and evolutionary algorithms. GECCO (Companion) (2019)
Sergio Contador, José Ignacio Hidalgo, Oscar Garnica, J. Manuel Velasco, Juan Lanchares
Can clustering improve glucose forecasting with genetic programming models? GECCO (Companion) (2019)
José Manuel Velasco, Oscar Garnica, Juan Lanchares, Marta Botella, José Ignacio Hidalgo
Combining data augmentation, EDAs and grammatical evolution for blood glucose forecasting. Memetic Comput. 10 (3) (2018)
José Manuel Velasco, Oscar Garnica, Sergio Contador, Marta Botella, Juan Lanchares, José Ignacio Hidalgo
Forecasting glucose levels in patients with diabetes mellitus using semantic grammatical evolution and symbolic aggregate approximation. GECCO (Companion) (2017)
José Manuel Velasco, Oscar Garnica, Sergio Contador, José Manuel Colmenar, Esther Maqueda, Marta Botella, Juan Lanchares, José Ignacio Hidalgo
Enhancing Grammatical Evolution Through Data Augmentation: Application to Blood Glucose Forecasting. EvoApplications (1) (2017)
José Ignacio Hidalgo, J. Manuel Colmenar, Gabriel Kronberger, Stephan M. Winkler, Oscar Garnica, Juan Lanchares
Data Based Prediction of Blood Glucose Concentrations Using Evolutionary Methods. J. Medical Syst. 41 (9) (2017)
José Manuel Velasco, Oscar Garnica, Sergio Contador, Juan Lanchares, Esther Maqueda, Marta Botella, José Ignacio Hidalgo
Data augmentation and evolutionary algorithms to improve the prediction of blood glucose levels in scarcity of training data. CEC (2017)
Josefa Díaz Álvarez, J. Manuel Colmenar, José L. Risco-Martín, Juan Lanchares, Oscar Garnica
Optimizing L1 cache for embedded systems through grammatical evolution. Soft Comput. 20 (6) (2016)
J. Manuel Colmenar, José Ignacio Hidalgo, Juan Lanchares, Oscar Garnica, José L. Risco-Martín, Iván Contreras, Almudena Sánchez, J. Manuel Velasco
Compilable Phenotypes: Speeding-Up the Evaluation of Glucose Models in Grammatical Evolution. EvoApplications (2) (2016)
Josefa Díaz Álvarez, J. Manuel Colmenar, José L. Risco-Martín, Juan Lanchares, Oscar Garnica
Optimizing Performance of L1 Cache Memory for Embedded Systems driven by Differential Evolution. GECCO (Companion) (2015)
J. Manuel Velasco, Stephan M. Winkler, José Ignacio Hidalgo, Oscar Garnica, Juan Lanchares, J. Manuel Colmenar, Esther Maqueda, Marta Botella, José Antonio Rubio
Data-Based Identification of Prediction Models for Glucose. GECCO (Companion) (2015)
José Ignacio Hidalgo, J. Manuel Colmenar, José Luis Risco-Martín, Carlos Sánchez-Lacruz, Juan Lanchares, Oscar Garnica, Josefa Díaz
Solving GA-hard problems with EMMRS and GPGPUs. GECCO (2014)
José Ignacio Hidalgo, J. Manuel Colmenar, José Luis Risco-Martín, Esther Maqueda, Marta Botella, José Antonio Rubio, Alfredo Cuesta-Infante, Oscar Garnica, Juan Lanchares
Clarke and parkes error grid analysis of diabetic glucose models obtained with evolutionary computation. GECCO (Companion) (2014)
José L. Risco-Martín, J. Manuel Colmenar, José Ignacio Hidalgo, Juan Lanchares, Josefa Díaz
A methodology to automatically optimize dynamic memory managers applying grammatical evolution. J. Syst. Softw. 91 (2014)
Juan Lanchares, Oscar Garnica, Francisco Fernández de Vega, José Ignacio Hidalgo
A review of bioinspired computer-aided design tools for hardware design. Concurr. Comput. Pract. Exp. 25 (8) (2013)
José L. Risco-Martín, Juan Lanchares, Carlos A. Coello Coello
Special issue on evolutionary computation on general purpose graphics processing units. Soft Comput. 16 (2) (2012)
Sonia López, Oscar Garnica, David H. Albonesi, Steven G. Dropsho, Juan Lanchares, José Ignacio Hidalgo
A phase adaptive cache hierarchy for SMT processors. Microprocess. Microsystems 35 (8) (2011)
José Ignacio Hidalgo, Francisco Fernández, Juan Lanchares, Erick Cantú-Paz, Albert Y. Zomaya
Parallel Architectures and Bioinspired Algorithms. Parallel Comput. 36 (10-11) (2010)
José Manuel Colmenar, José L. Risco-Martín, David Atienza, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares
Improving reliability of embedded systems through dynamic memory manager optimization using grammatical evolution. GECCO (2010)
J. Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo
Simulating a LAGS processor to consider variable latency on L1 D-Cache. SummerSim (2010)
Sonia López, Oscar Garnica, David H. Albonesi, Steven G. Dropsho, Juan Lanchares, José Ignacio Hidalgo
Adaptive Cache Memories for SMT Processors. DSD (2010)
José Luis Risco-Martín, José Ignacio Hidalgo, David Atienza, Juan Lanchares, Oscar Garnica
Mixed heuristic and mathematical programming using reference points for dynamic data types optimization in multimedia embedded systems. GECCO (2009)
Christos Baloukas, José Luis Risco-Martín, David Atienza, Christophe Poucet, Lazaros Papadopoulos, Stylianos Mamagkakis, Dimitrios Soudris, José Ignacio Hidalgo, Francky Catthoor, Juan Lanchares
Optimization methodology of dynamic data structures based on genetic algorithms for multimedia embedded systems. J. Syst. Softw. 82 (4) (2009)
José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo
Characterizing asynchronous variable latencies through probability distribution functions. Microprocess. Microsystems 33 (7-8) (2009)
José L. Risco-Martín, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, David Atienza
Particle swarm optimisation of memory usage in embedded systems. Int. J. High Perform. Syst. Archit. 1 (4) (2008)
José L. Risco-Martín, José Ignacio Hidalgo, Juan Lanchares, Oscar Garnica
Solving discrete deceptive problems with EMMRS. GECCO (2008)
José Luis Risco-Martín, David Atienza, José Ignacio Hidalgo, Juan Lanchares
Design Flow of Dynamically-Allocated Data Types in Embedded Applications Based on Elitist Evolutionary Computation Optimization. DSD (2008)
José L. Risco-Martín, David Atienza, José Ignacio Hidalgo, Juan Lanchares
A parallel evolutionary algorithm to optimize dynamic data types in embedded systems. Soft Comput. 12 (12) (2008)
José L. Risco-Martín, Saurabh Mittal, David Atienza, José Ignacio Hidalgo, Juan Lanchares
Optimization of dynamic data types in embedded systems using DEVS/SOA-based modeling and simulation. Infoscale (2008)
José Ignacio Hidalgo, José L. Risco-Martín, David Atienza, Juan Lanchares
Analysis of multi-objective evolutionary algorithms to optimize dynamic data types in embedded systems. GECCO (2008)
José Manuel Colmenar, Noelia Morón, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo
Modelling Asynchronous Systems using Probability Distribution Functions. PDP (2008)
José Ignacio Hidalgo, Francisco Fernández de Vega, Juan Lanchares, Daniel Lombraña Gonzalez
Is the island model fault tolerant? GECCO (2007)
José Ignacio Hidalgo, Juan Lanchares, Francisco Fernández de Vega, Daniel Lombraña Gonzalez
Is the island model fault tolerant? GECCO (Companion) (2007)
David Atienza, Christos Baloukas, Lazaros Papadopoulos, Christophe Poucet, Stylianos Mamagkakis, José Ignacio Hidalgo, Francky Catthoor, Dimitrios Soudris, Juan Lanchares
Optimization of dynamic data structures in multimedia embedded systems using evolutionary computation. SCOPES (2007)
Sonia López, Steve Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares
Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches. HiPEAC (2007)
Guadalupe Miñana, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar, Oscar Garnica, Sonia López
Reducing power of functional units in high-performance processors by checking instruction codes and resizing adders. IET Comput. Digit. Tech. 1 (2) (2007)
Sonia López, Steven G. Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares
Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors. PACT (2007)
Guadalupe Miñana, José Ignacio Hidalgo, Oscar Garnica, Juan Lanchares, José Manuel Colmenar, Sonia López
A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors. PATMOS (2006)
José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López
Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart. DSD (2006)
Guadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar
A Power-Aware Technique for Functional Units in High-Performance Processors. DSD (2006)
José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López
Sim-async: An Architectural Simulator for Asynchronous Processor Modeling Using Distribution Functions. Euro-Par (2006)
Guadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar
Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width. PATMOS (2005)
José Manuel Colmenar, Oscar Garnica, Sonia López, José Ignacio Hidalgo, Juan Lanchares, Román Hermida
Empirical Characterization of the Latency of Long Asynchronous Pipelines with Data-Dependent Module Delays. PDP (2004)
Francisco Fernández, José Ignacio Hidalgo, Juan Lanchares, J. M. Sánchez
A methodology for reconfigurable hardware design based upon evolutionary computation. Microprocess. Microsystems 28 (7) (2004)
Juan de Vicente, Juan Lanchares, Román Hermida
Annealing placement by thermodynamic combinatorial optimization. ACM Trans. Design Autom. Electr. Syst. 9 (3) (2004)
Sonia López, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, Román Hermida
Power-Consumption RRRRreduction in Asynchronous Circuits Using Delay Path Unequalization. PATMOS (2003)
José Ignacio Hidalgo, Manuel Prieto, Juan Lanchares, Ranieri Baraglia, Francisco Tirado, Oscar Garnica
Hybrid Parallelization of a Compact Genetic Algorithm. PDP (2003)
José Ignacio Hidalgo, Francisco Fernández, Juan Lanchares, Juan Manuel Sánchez-Pérez, Román Hermida, Marco Tomassini, Ranieri Baraglia, Raffaele Perego, Oscar Garnica
Multi-FPGA Systems Synthesis by Means of Evolutionary Computation. GECCO (2003)
José Ignacio Hidalgo, Juan Lanchares, Aitor Ibarra, Román Hermida
A Hybrid Evolutionary Algorithm for Multi-FPGA Systems Design. DSD (2002)
Aitor Ibarra, Juan Lanchares, Jose Manuel Mendias, José Ignacio Hidalgo, Román Hermida
Transformation of Equational Specification by Means of Genetic Programming. EuroGP (2002)
Oscar Garnica, Juan Lanchares, Román Hermida
Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation. Fundam. Informaticae 50 (2) (2002)
Oscar Garnica, Juan Lanchares, Román Hermida
A New Methodology to Design Low-Power Asynchronous Circuits. PATMOS (2002)
Aitor Ibarra, José M. Mendías, Juan Lanchares, José Ignacio Hidalgo, Román Hermida
Optimization of Equational Specifications Using Genetic Techniques. DSD (2002)
Juan de Vicente, Juan Lanchares, Román Hermida
FPGA Placement by Thermodynamic Combinatorial Optimization. DATE (2002)
Oscar Garnica, Juan Lanchares, Román Hermida
Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation. ACSD (2001)
Oscar Garnica, Juan Lanchares, Román Hermida
A pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits. DATE (2001)
Ranieri Baraglia, Raffaele Perego, José Ignacio Hidalgo, Juan Lanchares, Francisco Tirado
A Parallel Compact Genetic Algorithm for Multi-FPGA Partitioning. PDP (2001)
Aitor Ibarra, Juan Lanchares, José Ignacio Hidalgo, F. Saenz
Pipelined Genetic Architecture with Fitness on the Fly. DSD (2001)
Juan de Vicente, Juan Lanchares, Román Hermida
Adaptive FPGA Placement by Natural Optimization. IEEE International Workshop on Rapid System Prototyping (2000)
José Ignacio Hidalgo, Juan Lanchares, Román Hermida
Partitioning and Placement for Multi-FPGA Systems Using Genetic Algorithms. EUROMICRO (2000)
José Ignacio Hidalgo, Manuel Prieto, Juan Lanchares, Francisco Tirado, B. de Andrés, Segundo Esteban San Roman, D. Rivera
A Method for Model Parameter Identification Using Parallel Genetic Algorithms. PVM/MPI (1999)
Juan de Vicente, Juan Lanchares, Román Hermida
Placement Optimization Based on Global Routing Updating for System Partitioning onto Multi-FPGA Mesh Topologies. FPL (1999)
Juan de Vicente, Juan Lanchares, Román Hermida
RSR: A New Rectilinear Steiner Minimum Tree Approximation for FPGA Placement and Global Routing. EUROMICRO (1998)
José Ignacio Hidalgo, Juan Lanchares
Functional Partitioning for Hardware-Software Codesign using Genetic Algorithms. EUROMICRO (1997)