José M. Mendías

Publication Activity (10 Years)

Years Active: 1996-2013
Publications (10 Years): 0

Top Topics

Wireless Transmission

Delay Insensitive

Vlsi Architecture

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Alberto A. Del Barrio, Seda Ogrenci Memik, María C. Molina, José M. Mendías, Román Hermida
A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths. Integr. 46 (2) (2013)
Alberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik, José M. Mendías, María C. Molina
Multispeculative Addition Applied to Datapath Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (12) (2012)
Alberto A. Del Barrio, Seda Ogrenci Memik, María C. Molina, José M. Mendías, Román Hermida
Power optimization in heterogenous datapaths. DATE (2011)
María C. Molina, Rafael Ruiz-Sautua, Pedro Garcia-Repetto, José M. Mendías
Performance-driven scheduling of behavioural specifications. Integr. 42 (3) (2009)
Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida
Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis CoRR (2007)
Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida
Pre-synthesis optimization of multiplications to improve circuit performance. DATE (2006)
Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida
Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis. DATE (2005)
Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida
Arrival time aware scheduling to minimize clock cycle length. ASP-DAC (2005)
Marc Leeman, David Atienza, Geert Deconinck, Vincenzo De Florio, José M. Mendías, Chantal Ykman-Couvreur, Francky Catthoor, Rudy Lauwereins
Methodology for Refinement and Optimisation of Dynamic Memory Management for Embedded Systems in Multimedia Applications. J. VLSI Signal Process. 40 (3) (2005)
Stylianos Mamagkakis, Christos Baloukas, David Atienza, Francky Catthoor, Dimitrios Soudris, José M. Mendías, Antonios Thanailakis
Reducing Memory Fragmentation with Performance-Optimized Dynamic Memory Allocators in Network Applications. WWIC (2005)
María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida
Behavioural Bitwise Scheduling Based on Computational Effort Balancing. DATE (2004)
Edgar G. Daylight, David Atienza, Arnout Vandecappelle, Francky Catthoor, José M. Mendías
Memory-access-aware data structure transformations for embedded software with dynamic data accesses. IEEE Trans. Very Large Scale Integr. Syst. 12 (3) (2004)
María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida
Behavioural Scheduling to Balance the Bit-Level Computational Effort. ISVLSI (2004)
María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida
Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis. PATMOS (2003)
María C. Molina, José M. Mendías, Román Hermida
Allocation of multiple precision behaviors for maximal bit level reuse of hardware resources. J. Syst. Archit. 49 (12-15) (2003)
María C. Molina, José M. Mendías, Román Hermida
High-Level Allocation to Minimize Internal Hardware Wastage. DATE (2003)
María C. Molina, José M. Mendías, Román Hermida
Bit-level scheduling of heterogeneous behavioural specifications. ICCAD (2002)
Olga Peñalba, José M. Mendías, Román Hermida
Source Code Transformation to Improve Conditional Hardware Reuse. DSD (2002)
María C. Molina, José M. Mendías, Román Hermida
Bit-Level Allocation of Multiple-Precision Specifications. DSD (2002)
Olga Peñalba, José M. Mendías, Román Hermida
Maximizing Conditonal Reuse by Pre-Synthesis Transformations. DATE (2002)
José M. Mendías, Román Hermida, María C. Molina, Olga Peñalba
Efficient Verification of Scheduling, Allocation and Binding in High-Level Synthesis. DSD (2002)
José M. Mendías, Román Hermida, Olga Peñalba
A study about the efficiency of formal high-level synthesis applied to verification. Integr. 31 (2) (2002)
Olga Peñalba, José M. Mendías, Román Hermida
A global approach to improve conditional hardware reuse in high-level synthesis. J. Syst. Archit. 47 (12) (2002)
María C. Molina, José M. Mendías, Román Hermida
Multiple-Precision Circuits Allocation Independent of Data-Objects Length. DATE (2002)
Aitor Ibarra, José M. Mendías, Juan Lanchares, José Ignacio Hidalgo, Román Hermida
Optimization of Equational Specifications Using Genetic Techniques. DSD (2002)
María C. Molina, José M. Mendías, Román Hermida
High-level synthesis of multiple-precision circuitsindependent of data-objects length. DAC (2002)
Olga Peñalba, José M. Mendías, María C. Molina
Execution Condition Analysis in High Level Synthesis: A Unified Approach. ISSS (2000)
Olga Peñalba, José M. Mendías, Román Hermida
A Unified Algorithm for Mutual Exclusiveness Identification. EUROMICRO (1999)
José M. Mendías, Román Hermida
Correct High-Level Synthesis: a Formal Perspective. DATE (1998)
José M. Mendías, Román Hermida, Milagros Fernández
Formal Techniques for Hardware Allocation. VLSI Design (1997)
José M. Mendías, Román Hermida, Milagros Fernández
Algebraic Support for Transformational Hardware Allocation. ED&TC (1996)