Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis.

María C. Molina Rafael Ruiz-Sautua José M. Mendías Román Hermida

Published in: PATMOS (2003)

Keyphrases

low power
power consumption
high level synthesis
low cost
high speed
single chip
high power
low power consumption
digital signal processing
logic circuits
vlsi architecture
wireless transmission
gate array
power dissipation
optimal allocation
image sensor
cmos technology
stereo matching