Rafael Ruiz-Sautua

Publication Activity (10 Years)

Years Active: 2003-2009
Publications (10 Years): 0

Publications

María C. Molina, Rafael Ruiz-Sautua, Pedro Garcia-Repetto, Román Hermida
Frequent-Pattern-Guided Multilevel Decomposition of Behavioral Specifications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (1) (2009)
María C. Molina, Rafael Ruiz-Sautua, Alberto A. Del Barrio, Jose Manuel Mendias
Subword Switching Activity Minimization to Optimize Dynamic Power Consumption. IEEE Des. Test Comput. 26 (4) (2009)
María C. Molina, Rafael Ruiz-Sautua, Pedro Garcia-Repetto, José M. Mendías
Performance-driven scheduling of behavioural specifications. Integr. 42 (3) (2009)
Pedro Garcia-Repetto, María C. Molina, Rafael Ruiz-Sautua, Guillermo Botella Juan
Exploiting Internal Operation Patterns during the High-Level Synthesis of Time-Constrained Circuits. DSD (2008)
Rafael Ruiz-Sautua, María C. Molina, Jose Manuel Mendias
Exploiting Bit-Level Delay Calculations to Soften Read-After-Write Dependences in Behavioral Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (9) (2007)
María C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Román Hermida
Area optimization of multi-cycle operators in high-level synthesis. DATE (2007)
Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida
Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis CoRR (2007)
María C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Román Hermida
Bitwise scheduling to balance the computational cost of behavioral specifications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (1) (2006)
Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida
Pre-synthesis optimization of multiplications to improve circuit performance. DATE (2006)
Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida
Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis. DATE (2005)
Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida
Arrival time aware scheduling to minimize clock cycle length. ASP-DAC (2005)
Rafael Ruiz-Sautua, María C. Molina, Jose Manuel Mendias, Román Hermida
Performance-driven read-after-write dependencies softening in high-level synthesis. ICCAD (2005)
María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida
Behavioural Bitwise Scheduling Based on Computational Effort Balancing. DATE (2004)
María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida
Behavioural Scheduling to Balance the Bit-Level Computational Effort. ISVLSI (2004)
María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida
Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis. PATMOS (2003)