A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths.
Alberto A. Del BarrioSeda Ogrenci MemikMaría C. MolinaJosé M. MendíasRomán HermidaPublished in: Integr. (2013)
Keyphrases
- low power
- high level synthesis
- low cost
- power consumption
- high speed
- single chip
- high power
- parallel architecture
- design space exploration
- digital signal processing
- low power consumption
- energy dissipation
- cmos technology
- wireless transmission
- real time
- vlsi circuits
- vlsi architecture
- image sensor
- mixed signal
- delay insensitive
- logic circuits
- power dissipation
- wireless networks