Simulating a LAGS processor to consider variable latency on L1 D-Cache.
J. Manuel ColmenarOscar GarnicaJuan LancharesJosé Ignacio HidalgoPublished in: SummerSim (2010)
Keyphrases
- prefetching
- cache misses
- hit ratio
- processor core
- embedded processors
- memory bandwidth
- replacement policy
- memory hierarchy
- response time
- memory subsystem
- web caching
- user perceived latency
- hit rate
- access patterns
- memory access
- shared memory multiprocessors
- single chip
- main memory
- database workloads
- high speed
- access latency
- parallel processing
- low latency
- server load
- web documents
- instruction set
- parallel processors
- high end
- multiprocessor systems
- read write
- ibm zenterprise
- multithreading
- query processing