A New Methodology to Design Low-Power Asynchronous Circuits.
Oscar GarnicaJuan LancharesRomán HermidaPublished in: PATMOS (2002)
Keyphrases
- low power
- delay insensitive
- asynchronous circuits
- single chip
- high speed
- low power consumption
- power consumption
- low cost
- logic circuits
- vlsi architecture
- digital signal processing
- ultra low power
- design process
- mixed signal
- design methodology
- gate array
- vlsi circuits
- power dissipation
- power reduction
- high power
- wireless transmission
- cmos technology
- signal processing
- image processing
- cmos image sensor
- nm technology
- design considerations