Reducing power of functional units in high-performance processors by checking instruction codes and resizing adders.
Guadalupe MiñanaJosé Ignacio HidalgoJuan LancharesJosé Manuel ColmenarOscar GarnicaSonia LópezPublished in: IET Comput. Digit. Tech. (2007)
Keyphrases
- functional units
- processing elements
- instruction set
- parallel computers
- parallel processing
- power consumption
- distributed memory
- parallel algorithm
- computer architecture
- random access
- machine learning
- parallel computing
- image processing algorithms
- parallel architectures
- parallel implementation
- multithreading
- hardware implementation
- floating point
- massively parallel
- parallel processors
- parallel architecture
- power dissipation
- fine grained