Mark Indovina

Publication Activity (10 Years)

Years Active: 2004-2023
Publications (10 Years): 10

Top Topics

Digital Signal Processors

Processing Elements

General Purpose Processors

Top Venues

ACM Great Lakes Symposium on VLSI

Publications

Purab Ranjan Sutradhar, Sathwika Bavikadi, Mark Indovina, Sai Manoj Pudukotai Dinakarrao, Amlan Ganguly
FlutPIM: : A Look-up Table-based Processing in Memory Architecture with Floating-point Computation Support for Deep Learning Applications. ACM Great Lakes Symposium on VLSI (2023)
Prangon Das, Purab Ranjan Sutradhar, Mark Indovina, Sai Manoj Pudukotai Dinakarrao, Amlan Ganguly
Implementation and Evaluation of Deep Neural Networks in Commercially Available Processing in Memory Hardware. SOCC (2022)
Sathwika Bavikadi, Purab Ranjan Sutradhar, Mark Indovina, Amlan Ganguly, Sai Manoj Pudukotai Dinakarrao
POLAR: Performance-aware On-device Learning Capable Programmable Processing-in-Memory Architecture for Low-Power ML Applications. DSD (2022)
Purab Ranjan Sutradhar, Sathwika Bavikadi, Mark Connolly, Savankumar Prajapati, Mark Indovina, Sai Manoj Pudukotai Dinakarrao, Amlan Ganguly
Look-up-Table Based Processing-in-Memory Architecture With Programmable Precision-Scaling for Deep Learning Applications. IEEE Trans. Parallel Distributed Syst. 33 (2) (2022)
Mark Connolly, Purab Ranjan Sutradhar, Mark Indovina, Amlan Ganguly
Flexible Instruction Set Architecture for Programmable Look-up Table based Processing-in-Memory. ICCD (2021)
Purab Ranjan Sutradhar, Mark Connolly, Sathwika Bavikadi, Sai Manoj Pudukotai Dinakarrao, Mark Indovina, Amlan Ganguly
pPIM: A Programmable Processor-in-Memory Architecture With Precision-Scaling for Deep Learning. IEEE Comput. Archit. Lett. 19 (2) (2020)
Rohini J. Gillela, Amlan Ganguly, Dorin Patru, Mark Indovina
The IANET Hardware Accelerator for Audio and Visual Data Classification. SoCC (2020)
Tanmay Shinde, Suryanarayanan Subramaniam, Padmanabh Deshmukh, M. Meraj Ahmed, Mark Indovina, Amlan Ganguly
A 0.24pJ/bit, 16Gbps OOK Transmitter Circuit in 45-nm CMOS for Inter and Intra-Chip Wireless Interconnects. ACM Great Lakes Symposium on VLSI (2018)
Abhishek Vashist, Amlan Ganguly, Mark Indovina
Testing WiNoC-Enabled Multicore Chips with BIST for Wireless Interconnects. NOCS (2018)
Suryanarayanan Subramaniam, Tanmay Shinde, Padmanabh Deshmukh, Md Shahriar Shamim, Mark Indovina, Amlan Ganguly
A 0.36pJ/bit, 17Gbps OOK receiver in 45-nm CMOS for inter and intra-chip wireless interconnects. SoCC (2017)
Christopher K. Lennard, Victor Berman, Saverio Fazzari, Mark Indovina, Cary Ussery, Marino Strik, John Wilson, Olivier Florent, François Rémond, Pierre Bricaud
Industrially proving the SPIRIT consortium specifications for design chain integration. DATE Designers' Forum (2006)
Wanli Liu, David H. Albonesi, John Gostomski, Lloyd Palum, Dave Hinterberger, Rick Wanzenried, Mark Indovina
An Evaluation of a Configurable Vliw Microarchitecture for Embedded Dsp Applications. J. Circuits Syst. Comput. 13 (6) (2004)