Dynamically managed multithreaded reconfigurable architectures for chip multiprocessors.

Matthew A. Watkins David H. Albonesi

Published in: PACT (2010)

Keyphrases

multithreading
multi core processors
power reduction
low cost
parallel computing
distributed memory
functional units
highly efficient
shared memory

heterogeneous computing
computational power
fine grain
field programmable gate array
reconfigurable architecture
parallel architectures
memory efficient
high density
systolic array

highly parallel
digital signal processors
changing environment
message passing
circuit design
single chip
coarse grained
interconnection networks
hardware and software

virtual environment
high speed
data partitioning
parallel programming
massively parallel
hardware implementation
reconfigurable hardware
general purpose
real time