Amit Golander

Publication Activity (10 Years)

Years Active: 2008-2023
Publications (10 Years): 4

Top Topics

High Compression

Memory Requirements

Foreseeable Future

Top Venues

IEEE Trans. Computers

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Roei Kisous, Amit Golander, Yigal Korman, Tim Gubner, Rune Humborstad, Manyi Lu
Near-Memory Processing Offload to Remote (Persistent) Memory. SYSTOR (2023)
Amit Golander, Shai Taharlev, Yigal Korman
pmAddr: a persistent memory centric computing architecture. SYSTOR (2022)
Amit Golander, Netanel Katzburg, Omer Zilberberg
Accelerating Unmodified Databases using Persistent Memory and Flash Storage Tiers. SYSTOR (2018)
Amit Golander, Sagi Manole, Yigal Korman
Persistent memory over fabric (PMoF). SYSTOR (2017)
Sagi Manole, Amit Golander, Shlomo Weiss
Protein Sequence Pattern Matching: Leveraging Application Specific Hardware Accelerators. IEEE Trans. Computers 63 (2) (2014)
Alexei Jolondz, Shlomo Weiss, Amit Golander
L1-L2 Interconnect Design Methodology and Arbitration in 3-D IC Multicore Compute Clusters. IEEE Trans. Very Large Scale Integr. Syst. 22 (10) (2014)
Amit Golander, Shai Tahar, Lior Glass, Giora Biran, Sagi Manole
Leveraging predefined huffman dictionaries for high compression rate and ratio. SYSTOR (2013)
Amit Golander, Shai Tahar, Lior Glass, Giora Biran, Sagi Manole
High Compression Rate and Ratio Using Predefined Huffman Dictionaries. DCC (2013)
Amit Golander, Nadav Levison, Omer Heymann, Alexander Briskman, Mark J. Wolski, Eric F. Robinson
A Cost-Efficient L1-L2 Multicore Interconnect: Performance, Power, and Area Considerations. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2011)
Amit Golander, Shlomo Weiss
Reexecution and Selective Reuse in Checkpoint Processors. Trans. High Perform. Embed. Archit. Compil. 2 (2009)
Amit Golander, Shlomo Weiss, Ronny Ronen
Synchronizing Redundant Cores in a Dynamic DMR Multicore Architecture. IEEE Trans. Circuits Syst. II Express Briefs (6) (2009)
Amit Golander, Shlomo Weiss
Checkpoint allocation and release. ACM Trans. Archit. Code Optim. 6 (3) (2009)
Amit Golander, Shlomo Weiss
Hiding the misprediction penalty of a resource-efficient high-performance processor. ACM Trans. Archit. Code Optim. 4 (4) (2008)
Amit Golander, Shlomo Weiss, Ronny Ronen
DDMR: Dynamic and Scalable Dual Modular Redundancy with Short Validation Intervals. IEEE Comput. Archit. Lett. 7 (2) (2008)
Hao Yu, Hubertus Franke, Giora Biran, Amit Golander, Terry Nelms, Brian M. Bass
Stateful hardware decompression in networking environment. ANCS (2008)