Micro-operation cache: a power aware frontend for variable instruction length ISA.
Baruch SolomonAvi MendelsonRonny RonenDoron OrensteinYoav AlmogPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2003)
Keyphrases
- back end
- memory hierarchy
- cache misses
- power consumption
- memory subsystem
- peak load
- instruction set
- electric vehicles
- prefetching
- multithreading
- query processing
- computational power
- multimedia
- speculative execution
- instruction set architecture
- ibm power processor
- shift register
- energy dissipation
- memory access
- power plant
- high speed