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A 35 fJ/bit-access sub-VT memory using a dual-bit area-optimized standard-cell in 65 nm CMOS.
Oskar Andersson
Babak Mohammadi
Pascal Andreas Meinerzhagen
Joachim Neves Rodrigues
Published in:
ESSCIRC (2014)
Keyphrases
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random access memory
analog to digital converter
high speed
random access
nm technology
design considerations
real time
virtual memory
digital libraries
low power
hash table
memory size
secondary storage
instruction set architecture