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Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS.
Pascal Andreas Meinerzhagen
Sandip Kundu
Andres Malavasi
Trang Nguyen
Muhammad M. Khellah
James W. Tschanz
Vivek De
Published in:
ESSCIRC (2019)
Keyphrases
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power dissipation
error detection and correction
flip flops
cmos technology
nm technology
power consumption
low power
error correction
data transmission
low voltage
digital signal processing
silicon on insulator
high speed
low cost
finite state machines
data acquisition
energy consumption