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Toward Functional Safety of Systolic Array-Based Deep Learning Hardware Accelerators.
Shamik Kundu
Suvadeep Banerjee
Arnab Raha
Suriyaprakash Natarajan
Kanad Basu
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2021)
Keyphrases
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deep learning
systolic array
reconfigurable architecture
data flow
unsupervised learning
machine learning
unsupervised feature learning
parallel architecture
weakly supervised
mental models
deep architectures
training data
learning algorithm
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