Shobha Vasudevan

Publication Activity (10 Years)

Years Active: 2004-2021
Publications (10 Years): 14

Top Topics

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Hardware Designs

Dynamic Analysis

Complete Coverage

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Shobha Vasudevan, Wenjie Jiang, David Bieber, Rishabh Singh, Hamid Shojaei, Richard Ho, Charles Sutton
Learning Semantic Representations to Verify Hardware Designs. NeurIPS (2021)
Debjit Pal, Shobha Vasudevan
Feature Engineering for Scalable Application-Level Post-Silicon Debugging. CoRR (2021)
Debjit Pal, Spencer Offenberger, Shobha Vasudevan
Assertion Ranking Using RTL Source Code Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (8) (2020)
Debjit Pal, Sai Ma, Shobha Vasudevan
Emphasizing Functional Relevance Over State Restoration in Post-Silicon Signal Tracing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (2) (2020)
Keven Feng, Sandeep Vora, Rui Jiang, Elyse Rosenbaum, Shobha Vasudevan
Guilty As Charged: Computational Reliability Threats Posed By Electrostatic Discharge-induced Soft Errors. DATE (2019)
Samuel Hertz, Debjit Pal, Spencer Offenberger, Shobha Vasudevan
A figure of merit for assertions in verification. ASP-DAC (2019)
Jiayi Duan, Ziheng Zeng, Alina Oprea, Shobha Vasudevan
Automated Generation and Selection of Interpretable Features for Enterprise Security. IEEE BigData (2018)
Debjit Pal, Abhishek Sharma, Sandip Ray, Flavio M. de Paula, Shobha Vasudevan
Application level hardware tracing for scaling post-silicon debug. DAC (2018)
Seyed Nematollah Ahmadyan, Suriyaprakash Natarajan, Shobha Vasudevan
A novel test compression algorithm for analog circuits to decrease production costs. Integr. 58 (2017)
Shobha Vasudevan
Still a Fight to Get It Right: Verification in the Era of Machine Learning. ICRC (2017)
Seyed Nematollah Adel Ahmadyan, Shobha Vasudevan
Automated Transient Input Stimuli Generation for Analog Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (5) (2016)
Debjit Pal, Shobha Vasudevan
Symptomatic Bug Localization for Functional Debug of Hardware Designs. VLSI Design (2016)
Seyed Nematollah Ahmadyan, Shobha Vasudevan
Duplex: simultaneous parameter-performance exploration for optimizing analog circuits. ICCAD (2016)
Seyed Nematollah Ahmadyan, Suriyaprakash Natarajan, Shobha Vasudevan
Every test makes a difference: Compressing analog tests to decrease production costs. ASP-DAC (2016)
Qiao Jin, Jiayi Duan, Shobha Vasudevan, Michael Bailey
Packer classifier based on PE header information. HotSoS (2015)
Seyed Nematollah Ahmadyan, Chenjie Gu, Suriyaprakash Natarajan, Eli Chiprout, Shobha Vasudevan
Fast eye diagram analysis for high-speed CMOS circuits. DATE (2015)
Sai Ma, Debjit Pal, Rui Jiang, Sandip Ray, Shobha Vasudevan
Can't See the Forest for the Trees: State Restoration's Limitations in Post-silicon Trace Signal Selection. ICCAD (2015)
Viraj Athavale, Sai Ma, Samuel Hertz, Shobha Vasudevan
Code Coverage of Assertions Using RTL Source Code Analysis. DAC (2014)
Lingyi Liu, Shobha Vasudevan
Scaling Input Stimulus Generation through Hybrid Static and Dynamic Analysis of RTL. ACM Trans. Design Autom. Electr. Syst. 20 (1) (2014)
Jayanand Asok Kumar, Seyed Nematollah Ahmadyan, Shobha Vasudevan
Efficient Statistical Model Checking of Hardware Circuits With Multiple Failure Regions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (6) (2014)
David Sheridan, Lingyi Liu, Hyungsul Kim, Shobha Vasudevan
A Coverage Guided Mining Approach for Automatic Generation of Succinct Assertions. VLSI Design (2014)
Seyed Nematollah Ahmadyan, Shobha Vasudevan
Reachability analysis of nonlinear analog circuits through iterative reachable set reduction. DATE (2013)
Jayanand Asok Kumar, Shobha Vasudevan
Formal Probabilistic Timing Verification in RTL. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (5) (2013)
Lingyi Liu, Xuanyu Zhong, Xiaotao Chen, Shobha Vasudevan
Diagnosing root causes of system level performance violations. ICCAD (2013)
Lingyi Liu, Shobha Vasudevan
Automatic Generation of System Level Assertions from Transaction Level Models. J. Electron. Test. 29 (5) (2013)
Samuel Hertz, David Sheridan, Shobha Vasudevan
Mining Hardware Assertions With Guidance From Static Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (6) (2013)
Chen-Hsuan Lin, Lingyi Liu, Shobha Vasudevan
Generating concise assertions with complete coverage. ACM Great Lakes Symposium on VLSI (2013)
Seyed Nematollah Ahmadyan, Jayanand Asok Kumar, Shobha Vasudevan
Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithm. DATE (2013)
Parth Sagdeo, Nicholas Ewalt, Debjit Pal, Shobha Vasudevan
Using automatically generated invariants for regression testing and bug localization. ASE (2013)
Lingyi Liu, Shobha Vasudevan
Scaling RTL property checking using feasible path analysisand decomposition. ACM Great Lakes Symposium on VLSI (2013)
Jayanand Asok Kumar, Kenneth M. Butler, Heesoo Kim, Shobha Vasudevan
Early prediction of NBTI effects using RTL source code analysis. DAC (2012)
Jayanand Asok Kumar, Shobha Vasudevan
Formal Performance Analysis for Faulty MIMO Hardware. IEEE Trans. Very Large Scale Integr. Syst. 20 (10) (2012)
Seyed Nematollah Ahmadyan, Jayanand Asok Kumar, Shobha Vasudevan
Goal-oriented stimulus generation for analog circuits. DAC (2012)
Lingyi Liu, David Sheridan, William Tuohy, Shobha Vasudevan
A Technique for Test Coverage Closure Using GoldMine. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (5) (2012)
Viraj Athavale, Sam Hertz, Darshan Jetly, Vijay Ganesan, Jim Krysl, Shobha Vasudevan
Using static analysis for coverage extraction fromemulation/prototyping platforms. CODES+ISSS (2012)
Jayanand Asok Kumar, Shobha Vasudevan
Verifying dynamic power management schemes using statistical model checking. ASP-DAC (2012)
Lingyi Liu, Chen-Hsuan Lin, Shobha Vasudevan
Word level feature discovery to enhance quality of assertion mining. ICCAD (2012)
Jayanand Asok Kumar, Shobha Vasudevan
Variation-Conscious Formal Timing Verification in RTL. VLSI Design (2011)
Hyungsul Kim, Sungjin Im, Tarek F. Abdelzaher, Jiawei Han, David Sheridan, Shobha Vasudevan
Signature Pattern Covering via Local Greedy Algorithm and Pattern Shrink. ICDM (2011)
Parth Sagdeo, Viraj Athavale, Sumant Kowshik, Shobha Vasudevan
PRECIS: Inferring invariants using program path guided clustering. ASE (2011)
Jayanand Asok Kumar, Lingyi Liu, Shobha Vasudevan
Scaling probabilistic timing verification of hardware using abstractions in design source code. FMCAD (2011)
Lingyi Liu, David Sheridan, William Tuohy, Shobha Vasudevan
Towards coverage closure: Using GoldMine assertions for generating design validation stimulus. DATE (2011)
Lingyi Liu, David Sheridan, Viraj Athavale, Shobha Vasudevan
Automatic generation of assertions from system level design using data mining. MEMOCODE (2011)
Lingyi Liu, Shobha Vasudevan
Efficient validation input generation in RTL by hybridized source code analysis. DATE (2011)
Shobha Vasudevan
Coverage closure in SoC verification: Are we chasing a mirage? VTS (2011)
Jayanand Asok Kumar, Shobha Vasudevan
Automatic Compositional Reasoning for Probabilistic Model Checking of Hardware Designs. QEST (2010)
Jayanand Asok Kumar, Shobha Vasudevan
Statistical guarantees of performance for MIMO designs. DSN (2010)
Shobha Vasudevan, David Sheridan, Sanjay J. Patel, David Tcheng, William Tuohy, Daniel R. Johnson
GoldMine: Automatic assertion generation using data mining and static analysis. DATE (2010)
Lingyi Liu, Shobha Vasudevan
STAR: Generating input vectors for design validation by static analysis of RTL. HLDVT (2009)
Vinod Viswanath, Shobha Vasudevan, Jacob A. Abraham
Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL. VLSI Design (2009)
Vinod Viswanath, Shobha Vasudevan, Jacob A. Abraham
Dedicated Rewriting: Automatic Verification of Low Power Transformations in Register Transfer Level. J. Low Power Electron. 5 (3) (2009)
Shobha Vasudevan, Vinod Viswanath, Jacob A. Abraham, Jiajin Tu
Sequential equivalence checking between system level and RTL descriptions. Des. Autom. Embed. Syst. 12 (4) (2008)
Shobha Vasudevan, Vinod Viswanath, Jacob A. Abraham
Efficient Microprocessor Verification using Antecedent Conditioned Slicing. VLSI Design (2007)
Shobha Vasudevan, Vinod Viswanath, Robert W. Sumners, Jacob A. Abraham
Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems. IEEE Trans. Computers 56 (10) (2007)
Shobha Vasudevan, E. Allen Emerson, Jacob A. Abraham
Improved verification of hardware designs through antecedent conditioned slicing. Int. J. Softw. Tools Technol. Transf. 9 (1) (2007)
Shobha Vasudevan, Jacob A. Abraham, Vinod Viswanath, Jiajin Tu
Automatic decomposition for sequential equivalence checking of system level and RTL descriptions. MEMOCODE (2006)
Sankar Gurumurthy, Shobha Vasudevan, Jacob A. Abraham
Automatic generation of instruction sequences targeting hard-to-detect structural faults in a processor. ITC (2006)
Shobha Vasudevan, E. Allen Emerson, Jacob A. Abraham
Efficient Model Checking of Hardware Using Conditioned Slicing. Electron. Notes Theor. Comput. Sci. 128 (6) (2005)
S. Guramurthy, Shobha Vasudevan, Jacob A. Abraham
Automated mapping of pre-computed module-level test sequences to processor instructions. ITC (2005)
Shobha Vasudevan, Jacob A. Abraham
Static program transformations for efficient software model checking. IFIP Congress Topical Sessions (2004)