Jayanand Asok Kumar

Publication Activity (10 Years)

Years Active: 2010-2014
Publications (10 Years): 0

Top Topics

Power Management

Formal Specification

Analog Circuits

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Jayanand Asok Kumar, Seyed Nematollah Ahmadyan, Shobha Vasudevan
Efficient Statistical Model Checking of Hardware Circuits With Multiple Failure Regions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (6) (2014)
Jayanand Asok Kumar, Shobha Vasudevan
Formal Probabilistic Timing Verification in RTL. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (5) (2013)
Seyed Nematollah Ahmadyan, Jayanand Asok Kumar, Shobha Vasudevan
Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithm. DATE (2013)
Jayanand Asok Kumar, Kenneth M. Butler, Heesoo Kim, Shobha Vasudevan
Early prediction of NBTI effects using RTL source code analysis. DAC (2012)
Jayanand Asok Kumar, Shobha Vasudevan
Formal Performance Analysis for Faulty MIMO Hardware. IEEE Trans. Very Large Scale Integr. Syst. 20 (10) (2012)
Seyed Nematollah Ahmadyan, Jayanand Asok Kumar, Shobha Vasudevan
Goal-oriented stimulus generation for analog circuits. DAC (2012)
Jayanand Asok Kumar, Shobha Vasudevan
Verifying dynamic power management schemes using statistical model checking. ASP-DAC (2012)
Jayanand Asok Kumar, Shobha Vasudevan
Variation-Conscious Formal Timing Verification in RTL. VLSI Design (2011)
Jayanand Asok Kumar, Lingyi Liu, Shobha Vasudevan
Scaling probabilistic timing verification of hardware using abstractions in design source code. FMCAD (2011)
Jayanand Asok Kumar, Shobha Vasudevan
Automatic Compositional Reasoning for Probabilistic Model Checking of Hardware Designs. QEST (2010)
Jayanand Asok Kumar, Shobha Vasudevan
Statistical guarantees of performance for MIMO designs. DSN (2010)