Formal Probabilistic Timing Verification in RTL.
Jayanand Asok KumarShobha VasudevanPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2013)
Keyphrases
- asynchronous circuits
- formal methods
- formal analysis
- probabilistic model
- bayesian networks
- model checking
- context sensitive
- database
- formal specification
- formal model
- generative model
- probabilistic approaches
- probabilistic logic
- uncertain data
- posterior probability
- information theoretic
- expert systems
- multiscale
- decision making
- learning algorithm
- information retrieval
- data mining
- real world