Verifying dynamic power management schemes using statistical model checking.
Jayanand Asok KumarShobha VasudevanPublished in: ASP-DAC (2012)
Keyphrases
- model checking
- temporal logic
- automated verification
- formal specification
- formal verification
- model checker
- finite state machines
- finite state
- partial order reduction
- timed automata
- temporal properties
- symbolic model checking
- pspace complete
- verification method
- reachability analysis
- formal methods
- bounded model checking
- asynchronous circuits
- transition systems
- epistemic logic
- power management
- reactive systems
- computation tree logic
- power consumption
- linear temporal logic
- satisfiability problem
- alternating time temporal logic