Efficient Statistical Model Checking of Hardware Circuits With Multiple Failure Regions.
Jayanand Asok KumarSeyed Nematollah AhmadyanShobha VasudevanPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2014)
Keyphrases
- model checking
- temporal logic
- temporal properties
- model checker
- finite state
- automated verification
- computation tree logic
- symbolic model checking
- asynchronous circuits
- partial order reduction
- formal verification
- formal specification
- finite state machines
- process algebra
- transition systems
- timed automata
- verification method
- bounded model checking
- reachability analysis
- reactive systems
- linear temporal logic
- formal methods
- deterministic finite automaton