Low power test application with selective compaction in VLSI designs.

Dariusz Czysz Janusz Rajski Jerzy Tyszer

Published in: ITC (2012)

Keyphrases

low power
high speed
single chip
vlsi circuits
power consumption
low cost
vlsi architecture
gate array
power dissipation
high power
low power consumption
digital signal processing
nm technology
real time
logic circuits
power reduction
video data