New test compression scheme based on low power BIST.
Jerzy TyszerMichal FilipekGrzegorz MrugalskiNilanjan MukherjeeJanusz RajskiPublished in: ETS (2013)
Keyphrases
- low power
- compression scheme
- power consumption
- low cost
- high speed
- image compression
- compression ratio
- data compression
- compression algorithm
- single chip
- built in self test
- logic circuits
- entropy coding
- vlsi architecture
- power reduction
- vlsi circuits
- image sensor
- low power consumption
- multiresolution
- rate distortion
- digital signal processing
- feature extraction
- mixed signal
- real time