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Star-EDT: Deterministic On-Chip Scheme Using Compressed Test Patterns.

Grzegorz MrugalskiJanusz RajskiLukasz RybakJedrzej SoleckiJerzy Tyszer
Published in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2017)
Keyphrases
  • high speed
  • low cost
  • vlsi implementation
  • relaxation algorithm
  • statistical significance
  • physical design
  • design patterns
  • data compression
  • temporal patterns
  • compressed domain
  • analog vlsi