Test generation for open and delay faults in CMOS circuits.
Cheng-Hung WuKuen-Jong LeeSudhakar M. ReddyPublished in: ITC-Asia (2017)
Keyphrases
- test generation
- test cases
- power dissipation
- mutation testing
- analog vlsi
- delay insensitive
- circuit design
- power consumption
- high speed
- test sequences
- design automation
- vlsi circuits
- low power
- cmos technology
- symbolic execution
- chip design
- software testing
- finite state machines
- quality assurance
- static analysis
- focal plane
- floating gate
- model based diagnosis
- fault diagnosis
- test data generation
- data sets
- artificial intelligence
- random access memory
- mixed signal
- low voltage
- digital signal processing
- test suite
- software systems
- low cost
- asynchronous circuits
- fault models
- test set
- object oriented
- built in self test