Wen-Ben Jone

Publication Activity (10 Years)

Years Active: 1989-2018
Publications (10 Years): 3

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

DAC

ISPD

J. Electron. Test.

Publications

Qiang Han, Qiang Xu, Wen-Ben Jone
SERA: statistical error rate analysis for profit-oriented performance binning of resilient circuits. Integr. 60 (2018)
Yin-Chi Peng, Chien-Chih Chen, Hsiang-Jen Tsai, Keng-Hao Yang, Pei-Zhe Huang, Shih-Chieh Chang, Wen-Ben Jone, Tien-Fu Chen
Leak Stopper: An Actively Revitalized Snoop Filter Architecture with Effective Generation Control. ACM Trans. Design Autom. Electr. Syst. 22 (3) (2017)
Hsuan-Ming Chou, Yi-Chiao Chen, Keng-Hao Yang, Jean Tsao, Shih-Chieh Chang, Wen-Ben Jone, Tien-Fu Chen
High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Protocols. IEEE Trans. Very Large Scale Integr. Syst. 24 (3) (2016)
Hsuan-Ming Chou, Ming-Yi Hsiao, Yi-Chiao Chen, Keng-Hao Yang, Jean Tsao, Chiao-Ling Lung, Shih-Chieh Chang, Wen-Ben Jone, Tien-Fu Chen
Soft-Error-Tolerant Design Methodology for Balancing Performance, Power, and Reliability. IEEE Trans. Very Large Scale Integr. Syst. 23 (9) (2015)
Qiang Han, Jianghao Guo, Qiang Xu, Wen-Ben Jone
On Resilient System Performance Binning. ISPD (2015)
Tak-Kei Lam, Xing Wei, Wen-Ben Jone, Yi Diao, Yu-Liang Wu
On macro-fault: a new fault model, its implications on fault tolerance and manufacturing yield. ACM Great Lakes Symposium on VLSI (2014)
Jianghao Guo, Qiang Han, Wen-Ben Jone, Yu-Liang Wu
A cross-layer fault-tolerant design method for high manufacturing yield and system reliability. DFTS (2013)
Feng Yuan, Yannan Liu, Wen-Ben Jone, Qiang Xu
On testing timing-speculative circuits. DAC (2013)
Qiang Han, Jianghao Guo, Wen-Ben Jone, Qiang Xu
Path delay testing in resilient system. MWSCAS (2013)
Hyoung-Kook Kim, Laung-Terng Wang, Yu-Liang Wu, Wen-Ben Jone
Testing of Synchronizers in Asynchronous FIFO. J. Electron. Test. 29 (1) (2013)
Rong Ye, Feng Yuan, Zelong Sun, Wen-Ben Jone, Qiang Xu
Post-placement voltage island generation for timing-speculative circuits. DAC (2013)
Shing-Yu Chen, Ming-Yi Hsiao, Wen-Ben Jone, Tien-Fu Chen
A configurable bus-tracer for error reproduction in post-silicon validation. VLSI-DAT (2013)
Shing-Yu Chen, Chi-Neng Wen, Geng-Hau Yang, Wen-Ben Jone, Tien-Fu Chen
IMITATOR: A deterministic multicore replay system with refining techniques. VLSI-DAT (2012)
Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Wen-Ben Jone, Michael S. Hsiao, Fangfang Li, James Chien-Mo Li, Jiun-Lang Huang
Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. ACM Trans. Design Autom. Electr. Syst. 17 (4) (2012)
Jason Nemeth, Rui Min, Wen-Ben Jone, Yiming Hu
Location Cache Design and Performance Analysis for Chip Multiprocessors. IEEE Trans. Very Large Scale Integr. Syst. 19 (1) (2011)
Hao Xu, Ranga Vemuri, Wen-Ben Jone
Dynamic Characteristics of Power Gating During Mode Transition. IEEE Trans. Very Large Scale Integr. Syst. 19 (2) (2011)
Hao Xu, Wen-Ben Jone, Ranga Vemuri
Hopping With Temperature and Process Variation. IEEE Trans. Very Large Scale Integr. Syst. 19 (7) (2011)
Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Zhigang Jiang, Lang Tan, Yu Zhang, Yu Hu, Wen-Ben Jone, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Lizhen Yu
Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (3) (2011)
Laung-Terng Wang, Xiaoqing Wen, Shianling Wu, Hiroshi Furukawa, Hao-Jan Chao, Boryau Sheu, Jianghao Guo, Wen-Ben Jone
Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (2) (2010)
Hao Xu, Ranga Vemuri, Wen-Ben Jone
Current shaping and multi-thread activation for fast and reliable power mode transition in multicore designs. ICCAD (2010)
Hao Xu, Wen-Ben Jone, Ranga Vemuri
th Hopping for Aggressive Runtime Leakage Control. J. Low Power Electron. 6 (3) (2010)
Shianling Wu, Laung-Terng Wang, Lizhen Yu, Hiroshi Furukawa, Xiaoqing Wen, Wen-Ben Jone, Nur A. Touba, FeiFei Zhao, Jinsong Liu, Hao-Jan Chao, Fangfang Li, Zhigang Jiang
Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains. DFT (2010)
Hao Xu, Wen-Ben Jone, Ranga Vemuri
Stretching the limit of microarchitectural level leakage control with Adaptive Light-Weight Vth Hopping. ICCAD (2010)
Hao Xu, Wen-Ben Jone, Ranga Vemuri
Novel Vth Hopping Techniques for Aggressive Runtime Leakage Control. VLSI Design (2010)
Hyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang
Fault Modeling and Analysis for Resistive Bridging Defects in a Synchronizer. J. Electron. Test. 26 (3) (2010)
Hyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang
Analysis of Resistive Open Defects in a Synchronizer. DFT (2009)
Hyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang, Shianling Wu
Analysis of Resistive Bridging Defects in a Synchronizer. Asian Test Symposium (2009)
Hao Xu, Ranga Vemuri, Wen-Ben Jone
Selective light Vth hopping (SLITH): Bridging the gap between runtime dynamic and leakage. DATE (2009)
Hao Xu, Ranga Vemuri, Wen-Ben Jone
Temporal and spatial idleness exploitation for optimal-grained leakage control. ICCAD (2009)
Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Wen-Ben Jone, Jianghao Guo, Kuen-Jong Lee, Wei-Shin Wang, Xiaoqing Wen, Hao-Jan Chao, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li
Turbo1500: Core-Based Design for Test and Diagnosis. IEEE Des. Test Comput. 26 (1) (2009)
Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone
Control Circuitry for Self-Repairable MEMS Accelerometers. EIAT/IETA (2008)
Hao Xu, Wen-Ben Jone, Ranga Vemuri
Accurate energy breakeven time estimation for run-time power gating. ICCAD (2008)
Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Kuen-Jong Lee, Xiaoqing Wen, Wen-Ben Jone, Chia-Hsien Yeh, Wei-Shin Wang, Hao-Jan Chao, Jianghao Guo, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li
Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard. ITC (2008)
Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone
Material Fatigue and Reliability of MEMS Accelerometers. DFT (2008)
Sunil R. Das, Altaf Hossain, Satyendra Biswas, Emil M. Petriu, Mansour H. Assaf, Wen-Ben Jone, Mehmet Sahinoglu
On a New Graph Theory Approach to Designing Zero-Aliasing Space Compressors for Built-In Self-Testing. IEEE Trans. Instrum. Meas. 57 (10) (2008)
Hao Xu, Ranga Vemuri, Wen-Ben Jone
Dynamic virtual ground voltage estimation for power gating. ISLPED (2008)
Hao Xu, Ranga Vemuri, Wen-Ben Jone
Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW. ICCD (2008)
Sunil R. Das, Jila Zakizadeh, Satyendra Biswas, Mansour H. Assaf, Amiya Nayak, Emil M. Petriu, Wen-Ben Jone, Mehmet Sahinoglu
Testing Analog and Mixed-Signal Circuits With Built-In Hardware - A New Approach. IEEE Trans. Instrum. Meas. 56 (3) (2007)
Jianxun Liu, Wen-Ben Jone
An efficient routing method for pseudo-exhaustive built-in self-testing of high-speed interconnects. ICCD (2007)
Wei Pei, Wen-Ben Jone, Yiming Hu
Fault Modeling and Detection for Drowsy SRAM Caches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (6) (2007)
Ming Li, Wen-Ben Jone, Qing-An Zeng
An Efficient Wrapper Scan Chain Configuration Method for Network-on-Chip Testing. ISVLSI (2006)
Ming Li, Qing-An Zeng, Wen-Ben Jone
DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip. DAC (2006)
Wei Pei, Wen-Ben Jone, Yiming Hu
Fault Modeling and Detection for Drowsy SRAM Caches. ITC (2006)
Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone
Reliability Analysis of Self-Repairable MEMS Accelerometer. DFT (2006)
Jianxun Liu, Wen-Ben Jone, Sunil R. Das
Crosstalk test pattern generation for dynamic programmable logic arrays. IEEE Trans. Instrum. Meas. 55 (4) (2006)
Sunil R. Das, Chittoor V. Ramamoorthy, Mansour H. Assaf, Emil M. Petriu, Wen-Ben Jone, Mehmet Sahinoglu
Revisiting response compaction in space for full-scan circuits with nonexhaustive test sets using concept of sequence characterization. IEEE Trans. Instrum. Meas. 54 (5) (2005)
Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone
A dual-mode built-in self-test technique for capacitive MEMS devices. IEEE Trans. Instrum. Meas. 54 (5) (2005)
Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone
Design and Analysis of Self-Repairable MEMS Accelerometer. DFT (2005)
Vinod Narayanan, Swaroop Ghosh, Wen-Ben Jone, Sunil R. Das
A built-in self-testing method for embedded multiport memory arrays. IEEE Trans. Instrum. Meas. 54 (5) (2005)
Cheng-Hung Lin, Yung-Chang Huang, Shih-Chieh Chang, Wen-Ben Jone
Design and design automation of rectification logic for engineering change. ASP-DAC (2005)
Sunil R. Das, Chittoor V. Ramamoorthy, Mansour H. Assaf, Emil M. Petriu, Wen-Ben Jone, Mehmet Sahinoglu
Fault simulation and response compaction in full scan circuits using HOPE. IEEE Trans. Instrum. Meas. 54 (6) (2005)
Swaroop Ghosh, K. W. Lai, Wen-Ben Jone, Shih-Chieh Chang
Scan Chain Fault Identification Using Weight-Based Codes for SoC Circuits. Asian Test Symposium (2004)
Rui Min, Wen-Ben Jone, Yiming Hu
Location cache: a low-power L2 cache system. ISLPED (2004)
Rui Min, Wen-Ben Jone, Yiming Hu
Phased tag cache: an efficient low power cache system. ISCAS (2) (2004)
Vikram Arora, Wen-Ben Jone, Der-Cheng Huang, Sunil R. Das
A parallel built-in self-diagnostic method for nontraditional faults of embedded memory arrays. IEEE Trans. Instrum. Meas. 53 (4) (2004)
Rui Min, Zhiyong Xu, Yiming Hu, Wen-Ben Jone
Partial Tag Comparison: A New Technology for Power-Efficient Set-Associative Cache Designs. VLSI Design (2004)
Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone
A Dual-Mode Built-In Self-Test Technique for Capacitive MEMS Devices. VTS (2004)
Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, I. P. Hsu, J.-Y. Chen
Design theory and implementation for low-power segmented bus systems. ACM Trans. Design Autom. Electr. Syst. 8 (1) (2003)
Wen-Ben Jone, Der-Chen Huang, Sunil R. Das
An efficient BIST method for non-traditional faults of embedded memory arrays. IEEE Trans. Instrum. Meas. 52 (5) (2003)
J. H. Jiang, Wen-Ben Jone, Shih-Chieh Chang, Swaroop Ghosh
Embedded core test generation using broadcast test architecture and netlist scrambling. IEEE Trans. Reliab. 52 (4) (2003)
Sunil R. Das, M. Sudarma, Mansour H. Assaf, Emil M. Petriu, Wen-Ben Jone, Krishnendu Chakrabarty, Mehmet Sahinoglu
Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with nonexhaustive test sets. IEEE Trans. Instrum. Meas. 52 (5) (2003)
Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, Kuen-Jong Lee
An efficient BIST method for distributed small buffers. IEEE Trans. Very Large Scale Integr. Syst. 10 (4) (2002)
Der-Cheng Huang, Wen-Ben Jone
A parallel transparent BIST method for embedded memory arrays bytolerating redundant operations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (5) (2002)
Sunil R. Das, Jing Yi Liang, Emil M. Petriu, Mansour H. Assaf, Wen-Ben Jone, Krishnendu Chakrabarty
Data compression in space under generalized mergeability based on concepts of cover table and frequency ordering. IEEE Trans. Instrum. Meas. 51 (1) (2002)
Der-Cheng Huang, Wen-Ben Jone
A parallel built-in self-diagnostic method for embedded memoryarrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (4) (2002)
Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das
A Parallel Built-In Self-Diagnostic Method For Embedded Memory Buffers. VLSI Design (2001)
Shih-Chieh Chang, Ching-Hwa Cheng, Wen-Ben Jone, Shin-De Lee, Jinn-Shyan Wang
Charge-sharing alleviation and detection for CMOS domino circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (2) (2001)
Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das
An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers. VLSI Design (2001)
Shih-Chieh Chang, Kwen-Yo Chen, Ching-Hsiang Cheng, Wen-Ben Jone, Sunil R. Das
Random Pattern Testability Enhancement by Circuit Rewiring. VLSI Design 2001 (4) (2001)
Wen-Ben Jone, Wu-Sung Yeh, Chingwei Yeh, Sunil R. Das
An adaptive path selection method for delay testing. IEEE Trans. Instrum. Meas. 50 (5) (2001)
Sunil R. Das, Chittoor V. Ramamoorthy, Mansour H. Assaf, Emil M. Petriu, Wen-Ben Jone
Fault tolerance in systems design in VLSI using data compression under constraints of failure probabilities. IEEE Trans. Instrum. Meas. 50 (6) (2001)
J. H. Jiang, Shih-Chieh Chang, Wen-Ben Jone
Embedded Core Testing Using Broadcast Test Architecture. DFT (2001)
Der-Cheng Huang, Wen-Ben Jone
An efficient parallel transparent diagnostic BIST. Asian Test Symposium (2000)
Shih-Chieh Chang, Wen-Ben Jone, Shi-Sen Chang
TAIR: testability analysis by implication reasoning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (1) (2000)
Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone
Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits. DFT (2000)
Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang
Charge sharing fault analysis and testing for CMOS domino logic circuits. Asian Test Symposium (2000)
Ching-Hwa Cheng, Shih-Chieh Chang, Shin-De Li, Wen-Ben Jone, Jinn-Shyan Wang
Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation. ICCAD (2000)
Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone
Charge Sharing Fault Analysis and Testing for CMOS Domino Logic Circuits. LATW (2000)
Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, Kuen-Jong Lee
An Efficient BIST Method for Small Buffers. VTS (1999)
Chingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone
Power reduction through iterative gate sizing and voltage scaling. ISCAS (1) (1999)
J.-Y. Chen, Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, Tien-Fu Chen
Segmented bus design for low-power systems. IEEE Trans. Very Large Scale Integr. Syst. 7 (1) (1999)
Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, Wen-Ben Jone
Charge Sharing Fault Detection for CMOS Domino Logic Circuits. DFT (1999)
Ching-Wei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone
Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications. DAC (1999)
Sunil R. Das, Nita Goel, Wen-Ben Jone, Amiya R. Nayak
Syndrome Signature in Output Compaction for VLSI Built-in Self-Test. VLSI Design 1998 (2) (1998)
Wen-Ben Jone, K. S. Tsai
Confidence analysis for defect-level estimation of VLSI random testing. ACM Trans. Design Autom. Electr. Syst. 3 (3) (1998)
Shih-Chieh Chang, Shi-Sen Chang, Wen-Ben Jone, Chien-Chung Tsai
A novel combinational testability analysis by considering signal correlation. ITC (1998)
Wen-Ben Jone, Sunil R. Das
A Stochastic Method for Defect Level Analysis of Pseudorandom Testing. VLSI Design (1998)
Wen-Ben Jone, Jiann-Chyi Rau, Shih-Chieh Chang, Yu-Liang Wu
A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits. ITC (1998)
Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das
Delay Fault Coverage Enhancement Using Multiple Test Observation Times. VLSI Design (1997)
Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das
Delay Fault Coverage Enhancement Using Variable Observation Times. J. Electron. Test. 11 (2) (1997)
Wen-Ben Jone, Nigam Shah, Anita Gleason, Sunil R. Das
PGEN: A Novel Approach to Sequential Circuit Test Generation. VLSI Design 4 (3) (1996)
Sunil R. Das, Nishith Goel, Wen-Ben Jone, Amiya R. Nayak
Syndrome signature in output compaction for VLSI BIST. VLSI Design (1996)
Dan Li, Wen-Ben Jone
Pseudorandom test-length analysis using differential solutions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (7) (1996)
Chen-Liang Fang, Wen-Ben Jone
Timing optimization by gate resizing and critical path identification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (2) (1995)
Wen-Ben Jone, Christos A. Papachristou
A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (3) (1995)
Wen-Ben Jone, Sunil R. Das
CACOP-a random pattern testability analyzer. IEEE Trans. Syst. Man Cybern. 25 (5) (1995)
Sunil R. Das, Wen-Ben Jone, Amiya R. Nayak, Ian Choi
On testing of sequential machines using circuit decomposition and stochastic modeling. IEEE Trans. Syst. Man Cybern. 25 (3) (1995)
Sunil R. Das, H. T. Ho, Wen-Ben Jone, Amiya R. Nayak
An improved output compaction technique for built-in self-test in VLSI circuits. VLSI Design (1995)
Wen-Ben Jone, Paresh Gondalia, Allan Gutjahr
Realizing a high measure of confidence for defect level analysis of random testing [VLSI]. IEEE Trans. Very Large Scale Integr. Syst. 3 (3) (1995)
Wen-Ben Jone, Cheng-Juei Wu
Multiple Fault Detection in Parity Checkers. IEEE Trans. Computers 43 (9) (1994)

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Publication Activity (10 Years)

Top Topics

Top Venues

Wen-Ben Jone