Segmented bus design for low-power systems.

J.-Y. Chen Wen-Ben Jone Jinn-Shyan Wang Hsueh-I Lu Tien-Fu Chen

Published in: IEEE Trans. Very Large Scale Integr. Syst. (1999)

Keyphrases

low power
high speed
single chip
power consumption
low cost
logic circuits
low power consumption
gate array
digital signal processing
power reduction
vlsi architecture
cmos technology
real time
power dissipation
high power
mixed signal
design methodology
ultra low power