Jinn-Shyan Wang

ORCID

Publication Activity (10 Years)

Years Active: 1995-2024
Publications (10 Years): 23

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

SoCC

ASICON

ASP-DAC

Publications

Jinn-Shyan Wang, Pei-Yuan Chou
Clock Period-Jitter Measurement With Low-Noise Runtime Calibration for Chips in FinFET CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (7) (2024)
Jinn-Shyan Wang, Yu-Hsuan Kuo
Design of synthesizable period-jitter sensor IP with high power reduction and variation resiliency. Integr. 97 (2024)
Tay-Jyi Lin, Yi-Hsuan Ting, Meng-Ze Hsu, Kuan-Han Lin, Chung-Ming Huang, Fu-Cheng Tsai, Shyh-Shyuan Sheu, Shih-Chieh Chang, Chingwei Yeh, Jinn-Shyan Wang
A 16 nm 140 TOPS/W 5 μJ/Inference Keyword Spotting Engine Based on 1D-BCNN. IEEE Trans. Circuits Syst. II Express Briefs 70 (12) (2023)
Tay-Jyi Lin, Chen-Zong Liao, You-Jia Hu, Wei-Cheng Hsu, Zheng-Xian Wu, Shao-Yu Wang, Chun-Ming Huang, Ying-Hui Lai, Chingwei Yeh, Jinn-Shyan Wang
A 40nm CMOS SoC for Real-Time Dysarthric Voice Conversion of Stroke Patients. ASP-DAC (2022)
Jinn-Shyan Wang, Chien-Tung Liu, Chao-Hsiang Wang
Low-Active-Energy and Low-Standby-Power Sub-threshold ROM for IoT Edge Sensing Systems. VLSI-DAT (2020)
Jinn-Shyan Wang, Cheng-Xin Xue, Chien-Tung Liu, Tay-Jyi Lin
A 0.21V 40nm NAND-ROM for IoT Sensing Systems with Long Standby Periods. ISCAS (2020)
Pei-Yuan Chou, Jinn-Shyan Wang
An All-Digital On-Chip Peak-to-Peak Jitter Measurement Circuit With Automatic Resolution Calibration for High PVT-Variation Resilience. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2019)
Chien-Tung Liu, Zhe-Wei Chang, Shih-Nung Wei, Jinn-Shyan Wang, Tay-Jyi Lin
A Low-Area, Low-Power, and Low-Leakage Error-Detecting Latch for Timing-Error Resilient System Designs. SoCC (2018)
Pei-Yuan Chou, Ya-Bei Fang, Bo-Hao Chen, Chien-Tung Liu, Tay-Jyi Lin, Jinn-Shyan Wang
Near-Threshold CORDIC Design with Dynamic Circuitry for Long-Standby IoT Applications. SoCC (2018)
Yung-Chen Chien, Jinn-Shyan Wang
A 0.2 V 32-Kb 10T SRAM With 41 nW Standby Power for IoT Applications. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2018)
Ya-Bei Fang, Pei-Yuan Chou, Bo-Hao Chen, Tay-Jyi Lin, Jinn-Shyan Wang
An all-n-type dynamic adder for ultra-low-leakage IoT devices. ASICON (2017)
Jinn-Shyan Wang, Shih-Nung Wei
Process/Voltage/Temperature-Variation-Aware Design and Comparative Study of Transition-Detector-Based Error-Detecting Latches for Timing-Error-Resilient Pipelined Systems. IEEE Trans. Very Large Scale Integr. Syst. 25 (10) (2017)
Po-Hao Wang, Yung-Chen Chien, Shang-Jen Tsai, Xuan-Yu Lin, Rizal Tanjung, Yi-Sian Lin, Shu-Wei Syu, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen
ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures. IEEE Trans. Very Large Scale Integr. Syst. 25 (12) (2017)
Yi-Hsuan Ting, Tay-Jyi Lin, Cheng-Chun Chang, Chih-Chien Hu, Chingwei Yeh, Jinn-Shyan Wang
Approximate Distributed Arithmetic for Variable-Latency Table Lookup. NGCAS (2017)
Yi-Hsuan Ting, Chih-Yang Wang, Yu-Sian Chang, Tay-Jyi Lin, Shih-Chieh Chang, Jinn-Shyan Wang
Overoptimistic voltage scaling in pre-error AVS systems and learning-based alleviation. SoCC (2016)
Ting-Yu Shyu, Bo-Yu Su, Tay-Jyi Lin, Chingwei Yeh, Jinn-Shyan Wang, Tien-Fu Chen
Variable-length VLIW encoding for code size reduction in embedded processors. SoCC (2016)
Po-Hao Wang, Wei-Chung Cheng, Yung-Hui Yu, Tang-Chieh Kao, Chi-Lun Tsai, Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen
Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations. IEEE Trans. Circuits Syst. II Express Briefs (10) (2016)
Shang-Yi Li, Pei-Yuan Chou, Jinn-Shyan Wang
Design of an all-digital temperature sensor in 28 nm CMOS using temperature-sensitive delay cells and adaptive-1P calibration for error reduction. ASP-DAC (2016)
Po-Hao Wang, Shang-Jen Tsai, Rizal Tanjung, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen
Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors. Integr. 54 (2016)
Jinn-Shyan Wang, Yung-Chen Chien, Fengzhi Liu, Pei-Yao Chang
A Calibration-Free PVTD-Variation-Tolerant Sensing Scheme for Footless-8T SRAM Designs. IEEE Trans. Multi Scale Comput. Syst. 1 (3) (2015)
Jinn-Shyan Wang, Chun-Yuan Cheng
An All-Digital Delay-Locked Loop Using an In-Time Phase Maintenance Scheme for Low-Jitter Gigahertz Operations. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2015)
Pei-Yuan Chou, I-Chen Wu, Jai-Wei Lin, Xuan-Yu Lin, Tien-Fu Chen, Tay-Jyi Lin, Jinn-Shyan Wang
Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches. ASICON (2015)
Jinn-Shyan Wang, Chun-Yuan Cheng, Pei-Yuan Chou, Tzu-Yi Yang
A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture. IEEE J. Solid State Circuits 50 (11) (2015)
Chun-Yuan Cheng, Jinn-Shyan Wang, Pei-Yuan Chou, Shiou-Ching Chen, Chi-Tien Sun, Yuan-Hua Chu, Tzu-Yi Yang
all-digital delay-locked loop in 65-nm CMOS. A-SSCC (2014)
Chung-Hsun Huang, Wei-Jen Chen, Keng-Jui Chang, Yi-Hsuan Ting, Keng-Chang Hsu, Yu-Fu Pan, Chao-Chun Chen, Yuan-Hua Chu, Tay-Jyi Lin, Jinn-Shyan Wang
Low power fixed-latency DSP accelerator with autonomous minimum energy tracking (AMET). Hot Chips Symposium (2014)
Jinn-Shyan Wang, Keng-Jui Chang, Chingwei Yeh, Shih-Chieh Chang
Embedding Repeaters in Silicon IPs for Cross-IP Interconnections. IEEE Trans. Very Large Scale Integr. Syst. 21 (3) (2013)
Po-Hao Wang, Wei-Chung Cheng, Yung-Hui Yu, Tang-Chieh Kao, Chi-Lun Tsai, Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen
Variation-aware and adaptive-latency accesses for reliable low voltage caches. VLSI-SoC (2013)
Jian-Shiun Chen, Chingwei Yeh, Jinn-Shyan Wang
Self-super-cutoff power gating with state retention on a 0.3V 0.29fJ/cycle/gate 32b RISC core in 0.13µm CMOS. ISSCC (2013)
Tzu-Yuan Kuo, Keng-Jui Chang, Jen-Hsiang Lee, Zong-Wu He, Jinn-Shyan Wang
An energy-efficient truly all-digital temperature sensor for SoC applications. ACM Great Lakes Symposium on VLSI (2013)
Yi-Mao Hsiao, Yuan-Sun Chu, Jeng-Farn Lee, Jinn-Shyan Wang
A high-throughput and high-capacity IPv6 routing lookup system. Comput. Networks 57 (3) (2013)
Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, Ting-Yu Shyu, Chien-Yung Chou, Shien-Chun Luo, Jiun-In Guo, Tien-Fu Chen, Gene C. H. Chuang, Yuan-Hua Chu, Liang-Chia Cheng, Hong-Men Su, Chewnpu Jou, Meikei Ieong, Cheng-Wen Wu, Jinn-Shyan Wang
A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. ISSCC (2013)
Chingwei Yeh, Yuan-Chang Chen, Jinn-Shyan Wang
Towards Process Variation-Aware Power Gating. IEEE Trans. Very Large Scale Integr. Syst. 20 (11) (2012)
Chieh-Jen Cheng, Chao-Ching Wang, Wei-Chun Ku, Tien-Fu Chen, Jinn-Shyan Wang
A Scalable High-Performance Virus Detection Processor Against a Large Pattern Set for Embedded Network Security. IEEE Trans. Very Large Scale Integr. Syst. 20 (5) (2012)
Chun-Yuan Cheng, Jinn-Shyan Wang, Cheng-Tai Yeh, Jenn-Shyan Sheu
Design of a 2.5-GHz, 3-ps jitter, 8-locking-cycle, all-digital delay-locked loop with cycle-by-cycle phase adjustment. VLSIC (2012)
Chun-Yuan Cheng, Jinn-Shyan Wang, Cheng-Tai Yeh
An ultra Low-voltage/Power-Efficient All-Digital Delay Locked Loop in 55 nm CMOS Technology. J. Circuits Syst. Comput. 21 (8) (2012)
Jinn-Shyan Wang, Pei-Yao Chang, Chi-Chang Lin
Design of 65 nm Sub-Threshold SRAM Using the Bitline Leakage Prediction Scheme and the Non-trimmed Sense Amplifier. IEICE Trans. Electron. (1) (2012)
Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, Yen-Hsiang Yu
A 4R/2W Register File Design for UDVS Microprocessors in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs (12) (2012)
Cheng-An Chien, Yao-Chang Yang, Hsiu-Cheng Chang, Jia-Wei Chen, Cheng-Yen Chang, Jiun-In Guo, Jinn-Shyan Wang, Ching-Hwa Cheng
A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video. ASP-DAC (2011)
Jinn-Shyan Wang, Keng-Jui Chang, Shu-Yi Yang, Tsung-Han Hsieh, Chingwei Yeh
RSCE-aware ultra-low-voltage 40-nm CMOS circuits. ISOCC (2011)
Jinn-Shyan Wang, Yung-Chen Chien, Jia-Hong Lin, Chun-Yuan Cheng, Ying-Ting Ma, Chung-Hsun Huang
ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designs. ASICON (2011)
Jia-Wei Chen, Hsiu-Cheng Chang, Jinn-Shyan Wang, Jiun-In Guo
A dynamic quality-adjustable H.264 intra coder. IEEE Trans. Consumer Electron. 57 (3) (2011)
Jinn-Shyan Wang, Tsung-Han Hsieh, Keng-Jui Chang, Chingwei Yeh
Low power shift registers for megabits CMOS image sensors. ASICON (2011)
Chingwei Yeh, Yan-Nan Liu, Jinn-Shyan Wang, Pei-Yao Chang
Variation-resilient voltage generation for SRAM weak cell testing. ASICON (2011)
Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh
Design of High-Performance CMOS Level Converters Considering PVT Variations. IEICE Trans. Electron. (5) (2011)
Jinn-Shyan Wang, Pei-Yao Chang, Tai-Shin Tang, Jia-Wei Chen, Jiun-In Guo
Design of Subthreshold SRAMs for Energy-Efficient Quality-Scalable Video Applications. IEEE J. Emerg. Sel. Topics Circuits Syst. 1 (2) (2011)
Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh
Heuristic Sizing Methodology for Designing High-Performance CMOS Level Converters with Balanced Rise and Fall Delays. IEICE Trans. Electron. (10) (2010)
Jinn-Shyan Wang, Chun-Yuan Cheng, Je-Ching Liu, Yu-Chia Liu, Yi-Ming Wang
A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop. IEEE J. Solid State Circuits 45 (5) (2010)
Jinn-Shyan Wang, Chun-Yuan Cheng, Je-Ching Liu, Yu-Chia Liu, Yi-Ming Wang
A 55nm 1GHz one-cycle-locking de-skewing circuit. ISCAS (2010)
Hsiu-Cheng Chang, Jia-Wei Chen, Bing-Tsung Wu, Ching-Lung Su, Jinn-Shyan Wang, Jiun-In Guo
A Dynamic Quality-Adjustable H.264 Video Encoder for Power-Aware Video Applications. IEEE Trans. Circuits Syst. Video Technol. 19 (12) (2009)
Hsiu-Cheng Chang, Jia-Wei Chen, Yao-Chang Yang, Cheng-An Chien, Tzu-Chun Chang, Jinn-Shyan Wang, Jiun-In Guo
A Dynamic Quality-scalable H.264 Video Encoder. ISCAS (2009)
Wei-Chun Ku, Shu-Hsuan Chou, Jui-Chin Chu, Chi-Lin Liu, Tien-Fu Chen, Jiun-In Guo, Jinn-Shyan Wang
VisoMT: A Collaborative Multithreading Multicore Processor for Multimedia Applications With a Fast Data Switching Mechanism. IEEE Trans. Circuits Syst. Video Technol. 19 (11) (2009)
Hsiu-Cheng Chang, Yao-Chang Yang, Jia-Wei Chen, Ching-Lung Su, Cheng-An Chien, Jiun-In Guo, Jinn-Shyan Wang
A dynamic quality-scalable H.264 video encoder chip. ASP-DAC (2009)
Shu-Hsuan Chou, Chien-Chih Chen, Chi-Neng Wen, Yi-Chao Chan, Tien-Fu Chen, Chao-Ching Wang, Jinn-Shyan Wang
No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips. DAC (2009)
Chao-Ching Wang, Chieh-Jen Cheng, Tien-Fu Chen, Jinn-Shyan Wang
An Adaptively Dividable Dual-Port BiTCAM for Virus-Detection Processors in Mobile Devices. IEEE J. Solid State Circuits 44 (5) (2009)
Chao-Ching Wang, Chieh-Jen Cheng, Tien-Fu Chen, Jinn-Shyan Wang
An Adaptively Dividable Dual-Port BiTCAM for Virus-Detection Processors in Mobile Devices. ISSCC (2008)
Tzu-Yuan Kuo, Jinn-Shyan Wang
A low-voltage latch-adder based tree multiplier. ISCAS (2008)
Chao-Ching Wang, Jinn-Shyan Wang, Chingwei Yeh
High-Speed and Low-Power Design Techniques for TCAM Macros. IEEE J. Solid State Circuits 43 (2) (2008)
Hsiu-Cheng Chang, Jia-Wei Chen, Ching-Lung Su, Yao-Chang Yang, Yao Li, Chun-Hao Chang, Ze-Min Chen, Wei-Sen Yang, Chien-Chang Lin, Ching-Wen Chen, Jinn-Shyan Wang, Jiun-In Guo
A 7mW-to-183mW Dynamic Quality-Scalable H.264 Video Encoder Chip. ISSCC (2007)
Chun-Hao Chang, Jia-Wei Chen, Hsiu-Cheng Chang, Yao-Chang Yang, Jinn-Shyan Wang, Jiun-In Guo
A Quality Scalable H.264/AVC Baseline Intra Encoder for High Definition Video Applicaitons. SiPS (2007)
Jinn-Shyan Wang, Jian-Shiun Chen, Yi-Ming Wang, Chingwei Yeh
A 230mV-to-500mV 375KHz-to-16MHz 32b RISC Core in 0.18μm CMOS. ISSCC (2007)
Chien-Chang Lin, Jia-Wei Chen, Hsiu-Cheng Chang, Yao-Chang Yang, Yi-Huan Ou-Yang, Ming-Chih Tsai, Jiun-In Guo, Jinn-Shyan Wang
A 160K Gates/4.5 KB SRAM H.264 Video Decoder for HDTV Applications. IEEE J. Solid State Circuits 42 (1) (2007)
Jinn-Shyan Wang, Yi-Ming Wang, Chun-Yuan Cheng, Yu-Chia Liu
An improved SAR controller for DLL applications. ISCAS (2006)
Chingwei Yeh, Chao-Ching Wang, Lin-Chi Lee, Jinn-Shyan Wang
A 124.8Msps, 15.6mW field-programmable variable-length codec for multimedia applications. DATE Designers' Forum (2006)
Jia-Wei Chen, Chun-Hao Chang, Chien-Chang Lin, Yi-Huan Yang, Jiun-In Guo, Jinn-Shyan Wang
A Condition-based Intra Prediction Algorithm for H.264/AVC. ICME (2006)
Jia-Wei Chen, Kuan-Hung Chen, Jinn-Shyan Wang, Jiun-In Guo
A performance-aware IP core design for multimode transform coding using scalable-DA algorithm. ISCAS (2006)
Jia-Wei Chen, Chien-Chang Lin, Jiun-In Guo, Jinn-Shyan Wang
Low Complexity Architecture Design of H.264 Predictive Pixel Compensator for HDTV Application. ICASSP (3) (2006)
Hung-Yu Li, Chia-Cheng Chen, Jinn-Shyan Wang, Chingwei Yeh
An AND-type match-line scheme for high-performance energy-efficient content addressable memories. IEEE J. Solid State Circuits 41 (5) (2006)
Chingwei Yeh, En-Feng Hsu, Kai-Wen Cheng, Jinn-Shyan Wang, Nai-Jen Chang
An 830mW, 586kbps 1024-bit RSA chip design. DATE Designers' Forum (2006)
Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang
A high-performance direct 2-D transform coding IP design for MPEG-4AVC/H.264. IEEE Trans. Circuits Syst. Video Technol. 16 (4) (2006)
Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh, Yuan-Hua Chu
Design of STR level converters for SoCs using the multi-island dual-VDD design technique. ISCAS (2006)
Jinn-Shyan Wang, Chao-Ching Wang, Chingwei Yeh
TCAM for IP-Address Lookup Using Tree-style AND-type Match Lines and Segmented Search Lines. ISSCC (2006)
Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Jia-Wei Chen
An Energy-Aware IP Core Design for the Variable-Length DCT/IDCT Targeting at MPEG4 Shape-Adaptive Transforms. IEEE Trans. Circuits Syst. Video Technol. 15 (5) (2005)
Jinn-Shyan Wang, Shiang-Jiun Lin, Chingwei Yeh
A low-power high-SFDR CMOS direct digital frequency synthesizer. ISCAS (2) (2005)
Kuan-Hung Chen, Kuo-Chuan Chao, Jinn-Shyan Wang, Yuan-Sun Chu, Jiun-In Guo
An efficient spurious power suppression technique (SPST) and its applications on MPEG-4 AVC/H.264 transform coding design. ISLPED (2005)
Yi-Ming Wang, Chang-Fen Hu, Yi-Jen Chen, Jinn-Shyan Wang
An all-digital pulsewidth control loop. ISCAS (2) (2005)
Jinn-Shyan Wang, Hung-Yu Li, Chingwei Yeh, Tien-Fu Chen
Design techniques for single-low-V/sub DD/ CMOS systems. IEEE J. Solid State Circuits 40 (5) (2005)
Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang
An efficient direct 2-D transform coding IP design for MPEG-4 AVC/H.264. ISCAS (5) (2005)
Yi-Ming Wang, Jinn-Shyan Wang
An all-digital 50% duty-cycle corrector. ISCAS (2) (2004)
Jinn-Shyan Wang, Chien-Nan Kuo, Tsung-Han Yang
Low-power fixed-width array multipliers. ISLPED (2004)
Jinn-Shyan Wang, Shang-Jyh Shieh, Ching-Wei Yeh, Yuan-Hsun Yeh
Pseudo-footless CMOS domino logic circuits for high-performance VLSI designs. ISCAS (2) (2004)
Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Tien-Fu Chen
A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms. ISCAS (2) (2004)
Yi-Ming Wang, Jinn-Shyan Wang
A low-power half-delay-line fast skew-compensation circuit. IEEE J. Solid State Circuits 39 (6) (2004)
Chung-Hsun Huang, Jinn-Shyan Wang, Chingwei Yeh, Chih-Jen Fang
The CMOS carry-forward adders. IEEE J. Solid State Circuits 39 (2) (2004)
Yi-Ming Wang, Jinn-Shyan Wang
A reliable low-power fast skew-compensation circuit. ASP-DAC (2004)
Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh
A power-aware SNR-progressive DCT/IDCT IP core design for multimedia transform coding. ICME (2004)
Hung-Cheng Wu, Tien-Fu Chen, Hung-Yu Li, Jinn-Shyan Wang
Energy Efficient Caching-on-Cache Architectures for Embedded Systems. J. Inf. Sci. Eng. 19 (5) (2003)
Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, I. P. Hsu, J.-Y. Chen
Design theory and implementation for low-power segmented bus systems. ACM Trans. Design Autom. Electr. Syst. 8 (1) (2003)
Chung-Hsun Huang, Jinn-Shyan Wang
High-performance and power-efficient CMOS comparators. IEEE J. Solid State Circuits 38 (2) (2003)
Yuan-Pao Hsu, Kao-Shing Hwang, Jinn-Shyan Wang
An Associative Architecture of CMAC for Mobile Robot Motion Control. J. Inf. Sci. Eng. 18 (2) (2002)
Po-Hui Yang, Jinn-Shyan Wang
Low-voltage pulsewidth control loops for SOC applications. IEEE J. Solid State Circuits 37 (10) (2002)
Chung-Hsun Huang, Jinn-Shyan Wang, Yan-Chao Huang
Design of high-performance CMOS priority encoders and incrementer/decrementers using multilevel lookahead and multilevel folding techniques. IEEE J. Solid State Circuits 37 (1) (2002)
Shang-Jyh Shieh, Jinn-Shyan Wang, Yuan-Hsun Yeh
A contention-alleviated static keeper for high-performance domino logic circuits. ICECS (2001)
Sheng-Yeh Lai, Jinn-Shyan Wang
A high-efficiency CMOS charge pump circuit. ISCAS (4) (2001)
Jinn-Shyan Wang, Ching-Rong Chang, Chingwei Yeh
Analysis and design of high-speed and low-power CMOS PLAs. IEEE J. Solid State Circuits 36 (8) (2001)
Shih-Chieh Chang, Ching-Hwa Cheng, Wen-Ben Jone, Shin-De Lee, Jinn-Shyan Wang
Charge-sharing alleviation and detection for CMOS domino circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (2) (2001)
Shang-Jyh Shieh, Jinn-Shyan Wang
Design of low-power domino circuits using multiple supply voltages. ICECS (2001)
Ching-Rong Chang, Jinn-Shyan Wang, Cheng-Hui Yang
Low-power and high-speed ROM modules for ASIC applications. IEEE J. Solid State Circuits 36 (10) (2001)
Chung-Hsun Huang, Jinn-Shyan Wang, Yan-Chao Huang
A high-speed CMOS incrementer/decrementer. ISCAS (4) (2001)
Jinn-Shyan Wang, Wayne Tseng, Hung-Yu Li
Low-power embedded SRAM with the current-mode write technique. IEEE J. Solid State Circuits 35 (1) (2000)
Po-Hui Yang, Jinn-Shyan Wang, Yi-Ming Wang
A 1-GHz low-power transposition memory using new pulse-clocked D flip-flops. ISCAS (2000)

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Publication Activity (10 Years)

Top Topics

Top Venues

Jinn-Shyan Wang