Login / Signup
Design of a 2.5-GHz, 3-ps jitter, 8-locking-cycle, all-digital delay-locked loop with cycle-by-cycle phase adjustment.
Chun-Yuan Cheng
Jinn-Shyan Wang
Cheng-Tai Yeh
Jenn-Shyan Sheu
Published in:
VLSIC (2012)
Keyphrases
</>
feedback loop
case study
user interface
software engineering
real time
neural network
multimedia
design process
wireless networks