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Cheng-Tai Yeh
Publication Activity (10 Years)
Years Active: 2012-2012
Publications (10 Years): 0
Top Topics
Cmos Technology
Leakage Current
Design Considerations
Top Venues
VLSIC
J. Circuits Syst. Comput.
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Publications
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Chun-Yuan Cheng
,
Jinn-Shyan Wang
,
Cheng-Tai Yeh
,
Jenn-Shyan Sheu
Design of a 2.5-GHz, 3-ps jitter, 8-locking-cycle, all-digital delay-locked loop with cycle-by-cycle phase adjustment.
VLSIC
(2012)
Chun-Yuan Cheng
,
Jinn-Shyan Wang
,
Cheng-Tai Yeh
An ultra Low-voltage/Power-Efficient All-Digital Delay Locked Loop in 55 nm CMOS Technology.
J. Circuits Syst. Comput.
21 (8) (2012)