An ultra Low-voltage/Power-Efficient All-Digital Delay Locked Loop in 55 nm CMOS Technology.
Chun-Yuan ChengJinn-Shyan WangCheng-Tai YehPublished in: J. Circuits Syst. Comput. (2012)
Keyphrases
- cmos technology
- low voltage
- power dissipation
- power consumption
- low power
- mixed signal
- high speed
- power management
- silicon on insulator
- energy efficiency
- parallel processing
- design methodology
- design considerations
- random access memory
- image sensor
- leakage current
- digital signal processing
- real time
- energy saving
- video sequences