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Heuristic Sizing Methodology for Designing High-Performance CMOS Level Converters with Balanced Rise and Fall Delays.
Jinn-Shyan Wang
Yu-Juey Chang
Chingwei Yeh
Published in:
IEICE Trans. Electron. (2010)
Keyphrases
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rise and fall
levels of abstraction
optimal solution
dynamic programming
high speed
coarse grained
power consumption
delay insensitive
scientific computing
high reliability
design methodology
solution quality
neural network
cost effective
simulated annealing
evolutionary algorithm
case study
decision trees