Chingwei Yeh

Publication Activity (10 Years)

Years Active: 1994-2023
Publications (10 Years): 6

Top Topics

Embedded Processors

Ischemic Stroke

High Dynamic Range Imaging

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Tay-Jyi Lin, Yi-Hsuan Ting, Meng-Ze Hsu, Kuan-Han Lin, Chung-Ming Huang, Fu-Cheng Tsai, Shyh-Shyuan Sheu, Shih-Chieh Chang, Chingwei Yeh, Jinn-Shyan Wang
A 16 nm 140 TOPS/W 5 μJ/Inference Keyword Spotting Engine Based on 1D-BCNN. IEEE Trans. Circuits Syst. II Express Briefs 70 (12) (2023)
Po-Han Chen, Tay-Jyi Lin, Chingwei Yeh, Pei-Zen Chang, Wei-Chang Li
Force-Sensing Intelligent Vise for Cutting Dynamics Monitoring in Machining. SENSORS (2023)
Tay-Jyi Lin, Chen-Zong Liao, You-Jia Hu, Wei-Cheng Hsu, Zheng-Xian Wu, Shao-Yu Wang, Chun-Ming Huang, Ying-Hui Lai, Chingwei Yeh, Jinn-Shyan Wang
A 40nm CMOS SoC for Real-Time Dysarthric Voice Conversion of Stroke Patients. ASP-DAC (2022)
Yi-Hsuan Ting, Tay-Jyi Lin, Cheng-Chun Chang, Chih-Chien Hu, Chingwei Yeh, Jinn-Shyan Wang
Approximate Distributed Arithmetic for Variable-Latency Table Lookup. NGCAS (2017)
Chao-Yang Chang, Chung-Hsun Huang, Hui-Fu Chen, Chingwei Yeh, Yuan-Sun Chu, Tay-Jyi Lin
A low complexity edge-preserved image compression algorithm for LCD overdrive. GCCE (2016)
Ting-Yu Shyu, Bo-Yu Su, Tay-Jyi Lin, Chingwei Yeh, Jinn-Shyan Wang, Tien-Fu Chen
Variable-length VLIW encoding for code size reduction in embedded processors. SoCC (2016)
Chingwei Yeh, Chen-Yao Tsai, Tay-Jyi Lin, Jiun-In Guo
Maintaining color fidelity for dual-shot HDR imaging. ICCE-TW (2014)
Jinn-Shyan Wang, Keng-Jui Chang, Chingwei Yeh, Shih-Chieh Chang
Embedding Repeaters in Silicon IPs for Cross-IP Interconnections. IEEE Trans. Very Large Scale Integr. Syst. 21 (3) (2013)
Jian-Shiun Chen, Chingwei Yeh, Jinn-Shyan Wang
Self-super-cutoff power gating with state retention on a 0.3V 0.29fJ/cycle/gate 32b RISC core in 0.13µm CMOS. ISSCC (2013)
Chingwei Yeh, Yuan-Chang Chen, Jinn-Shyan Wang
Towards Process Variation-Aware Power Gating. IEEE Trans. Very Large Scale Integr. Syst. 20 (11) (2012)
Jinn-Shyan Wang, Keng-Jui Chang, Shu-Yi Yang, Tsung-Han Hsieh, Chingwei Yeh
RSCE-aware ultra-low-voltage 40-nm CMOS circuits. ISOCC (2011)
Jinn-Shyan Wang, Tsung-Han Hsieh, Keng-Jui Chang, Chingwei Yeh
Low power shift registers for megabits CMOS image sensors. ASICON (2011)
Chingwei Yeh, Yan-Nan Liu, Jinn-Shyan Wang, Pei-Yao Chang
Variation-resilient voltage generation for SRAM weak cell testing. ASICON (2011)
Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh
Design of High-Performance CMOS Level Converters Considering PVT Variations. IEICE Trans. Electron. (5) (2011)
Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh
Maintaining performance on power gating of microprocessor functional units by using a predictive pre-wakeup strategy. ACM Trans. Archit. Code Optim. 8 (3) (2011)
Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh
Adaptive Pipeline voltage Scaling in High Performance Microprocessor. J. Circuits Syst. Comput. 19 (8) (2010)
Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh
Heuristic Sizing Methodology for Designing High-Performance CMOS Level Converters with Balanced Rise and Fall Delays. IEICE Trans. Electron. (10) (2010)
Chao-Ching Wang, Jinn-Shyan Wang, Chingwei Yeh
High-Speed and Low-Power Design Techniques for TCAM Macros. IEEE J. Solid State Circuits 43 (2) (2008)
Jinn-Shyan Wang, Jian-Shiun Chen, Yi-Ming Wang, Chingwei Yeh
A 230mV-to-500mV 375KHz-to-16MHz 32b RISC Core in 0.18μm CMOS. ISSCC (2007)
Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh
Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling. HiPEAC (2007)
Chingwei Yeh, Chao-Ching Wang, Lin-Chi Lee, Jinn-Shyan Wang
A 124.8Msps, 15.6mW field-programmable variable-length codec for multimedia applications. DATE Designers' Forum (2006)
De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang, Chingwei Yeh
Timing driven power gating. DAC (2006)
Hung-Yu Li, Chia-Cheng Chen, Jinn-Shyan Wang, Chingwei Yeh
An AND-type match-line scheme for high-performance energy-efficient content addressable memories. IEEE J. Solid State Circuits 41 (5) (2006)
Chingwei Yeh, En-Feng Hsu, Kai-Wen Cheng, Jinn-Shyan Wang, Nai-Jen Chang
An 830mW, 586kbps 1024-bit RSA chip design. DATE Designers' Forum (2006)
Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh
Power minimization for dynamic PLAs. IEEE Trans. Very Large Scale Integr. Syst. 14 (6) (2006)
Chi-Shong Wang, Chingwei Yeh
Performance-driven technology mapping with MSG partition and selective gate duplication. ACM Trans. Design Autom. Electr. Syst. 11 (4) (2006)
Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh, Yuan-Hua Chu
Design of STR level converters for SoCs using the multi-island dual-VDD design technique. ISCAS (2006)
Jinn-Shyan Wang, Chao-Ching Wang, Chingwei Yeh
TCAM for IP-Address Lookup Using Tree-style AND-type Match Lines and Segmented Search Lines. ISSCC (2006)
Jinn-Shyan Wang, Shiang-Jiun Lin, Chingwei Yeh
A low-power high-SFDR CMOS direct digital frequency synthesizer. ISCAS (2) (2005)
Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh
Power minimization for dynamic PLAs. ASP-DAC (2005)
Jinn-Shyan Wang, Hung-Yu Li, Chingwei Yeh, Tien-Fu Chen
Design techniques for single-low-V/sub DD/ CMOS systems. IEEE J. Solid State Circuits 40 (5) (2005)
Chung-Hsun Huang, Jinn-Shyan Wang, Chingwei Yeh, Chih-Jen Fang
The CMOS carry-forward adders. IEEE J. Solid State Circuits 39 (2) (2004)
Jinn-Shyan Wang, Ching-Rong Chang, Chingwei Yeh
Analysis and design of high-speed and low-power CMOS PLAs. IEEE J. Solid State Circuits 36 (8) (2001)
Chingwei Yeh, Yin-Shuin Kang
Cell-based layout techniques supporting gate-level voltage scaling for low power. IEEE Trans. Very Large Scale Integr. Syst. 9 (6) (2001)
Wen-Ben Jone, Wu-Sung Yeh, Chingwei Yeh, Sunil R. Das
An adaptive path selection method for delay testing. IEEE Trans. Instrum. Meas. 50 (5) (2001)
Chingwei Yeh, Yin-Shuin Kang
Cell-based layout techniques supporting gate-level voltage scaling for low power. IEEE Trans. Very Large Scale Integr. Syst. 8 (5) (2000)
Chingwei Yeh, Chin-Chao Chang, Jinn-Shyan Wang
A cell selection strategy for low power applications. ISCAS (6) (1999)
Chingwei Yeh, Yin-Shuin Kang
A simulated annealing based method supporting dual supply voltages in standard cell placement. ISCAS (1) (1999)
Chingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone
Power reduction through iterative gate sizing and voltage scaling. ISCAS (1) (1999)
Chingwei Yeh, Chi-Shong Wang
On the integration of partitioning and global routing for rectilinear placement problems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (1) (1996)
Chingwei Yeh, Lung-Tien Liu, Chung-Kuan Cheng, T. C. Hu, S. Ahmed, M. Liddel
Block-oriented programmable design with switching network interconnect. IEEE Trans. Very Large Scale Integr. Syst. 2 (1) (1994)