Tay-Jyi Lin

Publication Activity (10 Years)

Years Active: 2001-2023
Publications (10 Years): 15

Top Topics

Embedded Processors

Compression Algorithm

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Tay-Jyi Lin, Yi-Hsuan Ting, Meng-Ze Hsu, Kuan-Han Lin, Chung-Ming Huang, Fu-Cheng Tsai, Shyh-Shyuan Sheu, Shih-Chieh Chang, Chingwei Yeh, Jinn-Shyan Wang
A 16 nm 140 TOPS/W 5 μJ/Inference Keyword Spotting Engine Based on 1D-BCNN. IEEE Trans. Circuits Syst. II Express Briefs 70 (12) (2023)
Po-Han Chen, Tay-Jyi Lin, Chingwei Yeh, Pei-Zen Chang, Wei-Chang Li
Force-Sensing Intelligent Vise for Cutting Dynamics Monitoring in Machining. SENSORS (2023)
Tay-Jyi Lin, Chen-Zong Liao, You-Jia Hu, Wei-Cheng Hsu, Zheng-Xian Wu, Shao-Yu Wang, Chun-Ming Huang, Ying-Hui Lai, Chingwei Yeh, Jinn-Shyan Wang
A 40nm CMOS SoC for Real-Time Dysarthric Voice Conversion of Stroke Patients. ASP-DAC (2022)
Jinn-Shyan Wang, Cheng-Xin Xue, Chien-Tung Liu, Tay-Jyi Lin
A 0.21V 40nm NAND-ROM for IoT Sensing Systems with Long Standby Periods. ISCAS (2020)
Chien-Tung Liu, Zhe-Wei Chang, Shih-Nung Wei, Jinn-Shyan Wang, Tay-Jyi Lin
A Low-Area, Low-Power, and Low-Leakage Error-Detecting Latch for Timing-Error Resilient System Designs. SoCC (2018)
Pei-Yuan Chou, Ya-Bei Fang, Bo-Hao Chen, Chien-Tung Liu, Tay-Jyi Lin, Jinn-Shyan Wang
Near-Threshold CORDIC Design with Dynamic Circuitry for Long-Standby IoT Applications. SoCC (2018)
Ya-Bei Fang, Pei-Yuan Chou, Bo-Hao Chen, Tay-Jyi Lin, Jinn-Shyan Wang
An all-n-type dynamic adder for ultra-low-leakage IoT devices. ASICON (2017)
Po-Hao Wang, Yung-Chen Chien, Shang-Jen Tsai, Xuan-Yu Lin, Rizal Tanjung, Yi-Sian Lin, Shu-Wei Syu, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen
ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures. IEEE Trans. Very Large Scale Integr. Syst. 25 (12) (2017)
Yi-Hsuan Ting, Tay-Jyi Lin, Cheng-Chun Chang, Chih-Chien Hu, Chingwei Yeh, Jinn-Shyan Wang
Approximate Distributed Arithmetic for Variable-Latency Table Lookup. NGCAS (2017)
Chao-Yang Chang, Chung-Hsun Huang, Hui-Fu Chen, Chingwei Yeh, Yuan-Sun Chu, Tay-Jyi Lin
A low complexity edge-preserved image compression algorithm for LCD overdrive. GCCE (2016)
Yi-Hsuan Ting, Chih-Yang Wang, Yu-Sian Chang, Tay-Jyi Lin, Shih-Chieh Chang, Jinn-Shyan Wang
Overoptimistic voltage scaling in pre-error AVS systems and learning-based alleviation. SoCC (2016)
Ting-Yu Shyu, Bo-Yu Su, Tay-Jyi Lin, Chingwei Yeh, Jinn-Shyan Wang, Tien-Fu Chen
Variable-length VLIW encoding for code size reduction in embedded processors. SoCC (2016)
Tay-Jyi Lin, Ting-Yu Shyu
Speculative Lookahead for Energy-Efficient Microprocessors. IEEE Trans. Very Large Scale Integr. Syst. 24 (1) (2016)
Po-Hao Wang, Wei-Chung Cheng, Yung-Hui Yu, Tang-Chieh Kao, Chi-Lun Tsai, Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen
Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations. IEEE Trans. Circuits Syst. II Express Briefs (10) (2016)
Po-Hao Wang, Shang-Jen Tsai, Rizal Tanjung, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen
Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors. Integr. 54 (2016)
Pei-Yuan Chou, I-Chen Wu, Jai-Wei Lin, Xuan-Yu Lin, Tien-Fu Chen, Tay-Jyi Lin, Jinn-Shyan Wang
Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches. ASICON (2015)
Ye-Jyun Lin, Chia-Lin Yang, Jiao-Wei Huang, Tay-Jyi Lin, Chih-Wen Hsueh, Naehyuck Chang
System-Level Performance and Power Optimization for MPSoC: A Memory Access-Aware Approach. ACM Trans. Embed. Comput. Syst. 14 (1) (2015)
Chingwei Yeh, Chen-Yao Tsai, Tay-Jyi Lin, Jiun-In Guo
Maintaining color fidelity for dual-shot HDR imaging. ICCE-TW (2014)
Chung-Hsun Huang, Wei-Jen Chen, Keng-Jui Chang, Yi-Hsuan Ting, Keng-Chang Hsu, Yu-Fu Pan, Chao-Chun Chen, Yuan-Hua Chu, Tay-Jyi Lin, Jinn-Shyan Wang
Low power fixed-latency DSP accelerator with autonomous minimum energy tracking (AMET). Hot Chips Symposium (2014)
Po-Hao Wang, Wei-Chung Cheng, Yung-Hui Yu, Tang-Chieh Kao, Chi-Lun Tsai, Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen
Variation-aware and adaptive-latency accesses for reliable low voltage caches. VLSI-SoC (2013)
Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, Ting-Yu Shyu, Chien-Yung Chou, Shien-Chun Luo, Jiun-In Guo, Tien-Fu Chen, Gene C. H. Chuang, Yuan-Hua Chu, Liang-Chia Cheng, Hong-Men Su, Chewnpu Jou, Meikei Ieong, Cheng-Wen Wu, Jinn-Shyan Wang
A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. ISSCC (2013)
Shih-Hao Ou, Che-Wei Yeh, Tay-Jyi Lin, Chih-Wei Liu
A smart stream controller for efficient implementation of streaming applications on the heterogeneous multicore processor. ISCAS (2012)
Tay-Jyi Lin, Yu-Ting Kuo, Yu-Jung Tsai, Ting-Yu Shyu, Yuan-Hua Chu
Energy-efficient RISC design with on-demand circuit-level timing speculation. ASP-DAC (2012)
Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, Yen-Hsiang Yu
A 4R/2W Register File Design for UDVS Microprocessors in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs (12) (2012)
Shyang-Chyun Chen, Chao-Chuan Chen, Wen-Chi Guo, Tay-Jyi Lin, Ching-Wei Yeh
Complexity-effective Hilbert-Huang transform (HHT) IP for embedded real-time applications. ASP-DAC (2012)
Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu
Complexity-Aware Quantization and Lightweight VLSI Implementation of FIR Filters. EURASIP J. Adv. Signal Process. 2011 (2011)
Shu-Hsuan Chou, Chien-Chih Chen, Chi-Neng Wen, Tien-Fu Chen, Tay-Jyi Lin
Hierarchical circuit-switched NoC for multicore video processing. Microprocess. Microsystems 35 (2) (2011)
David Chih-Wei Chang, Tay-Jyi Lin, Chung-Ju Wu, Jenq Kuen Lee, Yuan-Hua Chu, An-Yeu Wu
Parallel Architecture Core (PAC) - the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools. J. Signal Process. Syst. 62 (3) (2011)
Shih-Hao Ou, Yen-Cheng Lin, Tay-Jyi Lin, Chih-Wei Liu
Improving energy efficiency of functional units by exploiting their data-dependent latency. ISCAS (2010)
Ye-Jyun Lin, Chia-Lin Yang, Tay-Jyi Lin, Jiao-Wei Huang, Naehyuck Chang
Hierarchical memory scheduling for multimedia MPSoCs. ICCAD (2010)
Yu-Ting Kuo, Tay-Jyi Lin, Yueh-Tai Li, Chih-Wei Liu
Design and Implementation of Low-Power ANSI S1.11 Filter Bank for Digital Hearing Aids. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2010)
Kuo-Chiang Chang, Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu
Complexity-effective dynamic range compression for digital hearing aids. ISCAS (2010)
Chi-Neng Wen, Shu-Hsuan Chou, Tien-Fu Chen, Tay-Jyi Lin
RunAssert: A non-intrusive run-time assertion for parallel programs debugging. DATE (2010)
Tay-Jyi Lin, Pi-Chen Hsiao, Chi-Hung Lin, Shu-Chang Kuo, Chou-Kun Lin, Yu-Ting Kuo, Chih-Wei Liu, Yuan-Hua Chu
Collaborative voltage scaling with online STA and variable-latency datapath. ACM Great Lakes Symposium on VLSI (2010)
Shin-Kai Chen, Tay-Jyi Lin, Chih-Wei Liu
Parallel object detection on multicore platforms. SiPS (2009)
Yu-Ting Kuo, Tay-Jyi Lin, Yueh-Tai Li, Chou-Kun Lin, Chih-Wei Liu
Ultra low-power ANSI S1.11 filter bank for digital hearing aids. ASP-DAC (2009)
Yu-Ting Kuo, Tay-Jyi Lin, Wei-Han Chang, Yueh-Tai Li, Chih-Wei Liu, Shuenn-Tsong Young
Complexity-effective auditory compensation for digital hearing aids. ISCAS (2008)
Jwo-An Lin, Yung-Chou Tsai, Tay-Jyi Lin, Yarsun Hsu
Cycle Stealing and Channel Management for On-Chip Networks. HPCC (2008)
Tay-Jyi Lin, Shin-Kai Chen, Yu-Ting Kuo, Chih-Wei Liu, Pi-Chen Hsiao
Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications. J. Signal Process. Syst. 51 (3) (2008)
Shih-Hao Ou, Tay-Jyi Lin, Xiang Sheng Deng, Zhi Hong Zhuo, Chih-Wei Liu
Multithreaded coprocessor interface for multi-core multimedia SoC. ASP-DAC (2008)
Shih-Hao Ou, Yi Cho, Tay-Jyi Lin, Chih-Wei Liu
Improving datapathutilization of programmable DSP with composite functional units. ISCAS (2008)
Shin-Kai Chen, Bing-Shiun Wang, Tay-Jyi Lin, Chih-Wei Liu
Rapid C to FPGA Prototyping with Multithreaded Emulation Engine. ISCAS (2007)
Pi-Chen Hsiao, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei Jen
Latency-Tolerant Virtual Cluster Architecture for VLIW DSP. ISCAS (2007)
Li-Chun Lin, Shih-Hao Ou, Tay-Jyi Lin, Siang-Den Deng, Chih-Wei Liu
Single-Issue 1500MIPS Embedded DSP with Ultra Compact Codes. ASP-DAC (2007)
Yu-Ting Kuo, Tay-Jyi Lin, Yueh-Tai Li, Wei-Han Chang, Chih-Wei Liu, Shuenn-Tsong Young
Design of ANSI S1.11 Filter Bank for Digital Hearing Aids. ICECS (2007)
Shih-Hao Ou, Tay-Jyi Lin, Chao-Wei Huang, Yu-Ting Kuo, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen
A 52mW 1200MIPS compact DSP for multi-core media SoC. ASP-DAC (2006)
Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chih-Wei Jen
A Compact DSP Core with Static Floating-Point Arithmetic. J. VLSI Signal Process. 42 (2) (2006)
Yu-Ting Kuo, Tay-Jyi Lin, Yi Cho, Chih-Wei Liu, Chein-Wei Jen
Programmable FIR filter with adder-based computing engine. ISCAS (2006)
Chia-Hsien Liu, Tay-Jyi Lin, Chie-Min Chao, Pi-Chen Hsiao, Li-Chun Lin, Shin-Kai Chen, Chao-Wei Huang, Chih-Wei Liu, Chein-Wei Jen
Hierarchical instruction encoding for VLIW digital signal processors. ISCAS (4) (2005)
Wei-Sheng Huang, Tay-Jyi Lin, Shih-Hao Ou, Chih-Wei Liu, Chein-Wei Jen
Pipelining technique for energy-aware datapaths. ISCAS (2) (2005)
Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen
A unified processor architecture for RISC & VLIW DSP. ACM Great Lakes Symposium on VLSI (2005)
Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei Jen
Architecture for area-efficient 2-D transform in H.264/AVC. ICME (2005)
Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen
A compact DSP core with static floating-point unit & its microcode generation. ACM Great Lakes Symposium on VLSI (2004)
Hung-Yueh Lin, Tay-Jyi Lin, Chie-Min Chao, Yen-Chin Liao, Chih-Wei Liu, Chein-Wei Jen
Static floating-point unit with implicit exponent tracking for embedded DSP. ISCAS (2) (2004)
Tay-Jyi Lin, Chin-Chi Chang, Chen-Chia Lee, Chein-Wei Jen
An Efficient VLIW DSP Architecture for Baseband Processing. ICCD (2003)
Tay-Jyi Lin, Tsung-Hsun Yang, Chein-Wei Jen
Coefficient optimization for area-effective multiplier-less FIR filters. ICME (2003)
Tay-Jyi Lin, Tsung-Hsun Yang, Chein-Wei Jen
Area-effective FIR filter design for multiplier-less implementation. ISCAS (5) (2003)
Tay-Jyi Lin, Chin-Chi Chang, Tsung-Hsun Yang, Yu-Ming Chang, Chien-Hung Lin, Chen-Chia Lee, Hung-Yueh Lin, Chein-Wei Jen
Performance evaluation of ring-structure register file in multimedia applications. ICME (2003)
Tay-Jyi Lin, Chein-Wei Jen
CASCADE - configurable and scalable DSP environment. ISCAS (4) (2002)
Tay-Jyi Lin, Chein-Wei Jen
An efficient 2-D DWT architecture via resource cycling. ISCAS (4) (2001)