Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches.
Pei-Yuan ChouI-Chen WuJai-Wei LinXuan-Yu LinTien-Fu ChenTay-Jyi LinJinn-Shyan WangPublished in: ASICON (2015)
Keyphrases
- low power
- low cost
- power dissipation
- nm technology
- energy dissipation
- transmission line
- single chip
- fault diagnosis
- cmos technology
- low voltage
- hardware and software
- real time
- power system
- digital signal processing
- vlsi architecture
- digital camera
- power reduction
- high speed
- energy consumption
- power consumption
- high power
- logic circuits
- embedded systems
- low power consumption
- wireless transmission
- image sensor
- normal operation
- scheduling algorithm
- highly efficient
- rfid tags
- mixed signal
- power supply
- vlsi circuits