Pei-Yuan Chou

Publication Activity (10 Years)

Years Active: 2014-2024
Publications (10 Years): 5

Top Topics

Error Reduction

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Jinn-Shyan Wang, Pei-Yuan Chou
Clock Period-Jitter Measurement With Low-Noise Runtime Calibration for Chips in FinFET CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (7) (2024)
Pei-Yuan Chou, Jinn-Shyan Wang
An All-Digital On-Chip Peak-to-Peak Jitter Measurement Circuit With Automatic Resolution Calibration for High PVT-Variation Resilience. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2019)
Pei-Yuan Chou, Ya-Bei Fang, Bo-Hao Chen, Chien-Tung Liu, Tay-Jyi Lin, Jinn-Shyan Wang
Near-Threshold CORDIC Design with Dynamic Circuitry for Long-Standby IoT Applications. SoCC (2018)
Ya-Bei Fang, Pei-Yuan Chou, Bo-Hao Chen, Tay-Jyi Lin, Jinn-Shyan Wang
An all-n-type dynamic adder for ultra-low-leakage IoT devices. ASICON (2017)
Shang-Yi Li, Pei-Yuan Chou, Jinn-Shyan Wang
Design of an all-digital temperature sensor in 28 nm CMOS using temperature-sensitive delay cells and adaptive-1P calibration for error reduction. ASP-DAC (2016)
Pei-Yuan Chou, I-Chen Wu, Jai-Wei Lin, Xuan-Yu Lin, Tien-Fu Chen, Tay-Jyi Lin, Jinn-Shyan Wang
Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches. ASICON (2015)
Jinn-Shyan Wang, Chun-Yuan Cheng, Pei-Yuan Chou, Tzu-Yi Yang
A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture. IEEE J. Solid State Circuits 50 (11) (2015)
Chun-Yuan Cheng, Jinn-Shyan Wang, Pei-Yuan Chou, Shiou-Ching Chen, Chi-Tien Sun, Yuan-Hua Chu, Tzu-Yi Yang
all-digital delay-locked loop in 65-nm CMOS. A-SSCC (2014)