Tien-Fu Chen

Publication Activity (10 Years)

Years Active: 1991-2024
Publications (10 Years): 18

Top Topics

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Ching Chang, Chiao-Tung Chan, Wei-Yao Wang, Wen-Chih Peng, Tien-Fu Chen
TimeDRL: Disentangled Representation Learning for Multivariate Time-Series. ICDE (2024)
Ching Chang, Chiao-Tung Chan, Wei-Yao Wang, Wen-Chih Peng, Tien-Fu Chen
TimeDRL: Disentangled Representation Learning for Multivariate Time-Series. CoRR (2023)
Chi-Lin Hsieh, Kuei-Chung Chang, Tien-Fu Chen
Adaptive Similarity-Aware Hyperparameter Tuners for Classification Tasks. IEEE Access 11 (2023)
Ching Chang, Wen-Chih Peng, Tien-Fu Chen
LLM4TS: Two-Stage Fine-Tuning for Time-Series Forecasting with Pre-Trained LLMs. CoRR (2023)
Hsiang-Jen Tsai, Chien-Chih Chen, Yin-Chi Peng, Ya-Han Tsao, Yen-Ning Chiang, Wei-Cheng Zhao, Meng-Fan Chang, Tien-Fu Chen
A Flexible Wildcard-Pattern Matching Accelerator via Simultaneous Discrete Finite Automata. IEEE Trans. Very Large Scale Integr. Syst. 25 (12) (2017)
Yin-Chi Peng, Chien-Chih Chen, Hsiang-Jen Tsai, Keng-Hao Yang, Pei-Zhe Huang, Shih-Chieh Chang, Wen-Ben Jone, Tien-Fu Chen
Leak Stopper: An Actively Revitalized Snoop Filter Architecture with Effective Generation Control. ACM Trans. Design Autom. Electr. Syst. 22 (3) (2017)
Win-San Khwa, Meng-Fan Chang, Jau-Yi Wu, Ming-Hsiu Lee, Tzu-Hsiang Su, Keng-Hao Yang, Tien-Fu Chen, Tien-Yen Wang, Hsiang-Pang Li, Matthew J. BrightSky, SangBum Kim, Hsiang-Lam Lung, Chung Lam
A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100× for Storage Class Memory Applications. IEEE J. Solid State Circuits 52 (1) (2017)
Meng-Fan Chang, Chien-Chen Lin, Albert Lee, Yen-Ning Chiang, Chia-Chen Kuo, Geng-Hau Yang, Hsiang-Jen Tsai, Tien-Fu Chen, Shyh-Shyuan Sheu
A 3T1R Nonvolatile TCAM Using MLC ReRAM for Frequent-Off Instant-On Filters in IoT and Big-Data Processing. IEEE J. Solid State Circuits 52 (6) (2017)
Keng-Hao Yang, Hsiang-Jen Tsai, Chia-Yin Li, Paul Jendra, Meng-Fan Chang, Tien-Fu Chen
eTag: Tag-Comparison in Memory to Achieve Direct Data Access based on eDRAM to Improve Energy Efficiency of DRAM Cache. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2017)
Po-Hao Wang, Yung-Chen Chien, Shang-Jen Tsai, Xuan-Yu Lin, Rizal Tanjung, Yi-Sian Lin, Shu-Wei Syu, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen
ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures. IEEE Trans. Very Large Scale Integr. Syst. 25 (12) (2017)
Hsiang-Jen Tsai, Keng-Hao Yang, Yin-Chi Peng, Chien-Chen Lin, Ya-Han Tsao, Meng-Fan Chang, Tien-Fu Chen
Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology. IEEE Trans. Very Large Scale Integr. Syst. 25 (3) (2017)
Ting-Yu Shyu, Bo-Yu Su, Tay-Jyi Lin, Chingwei Yeh, Jinn-Shyan Wang, Tien-Fu Chen
Variable-length VLIW encoding for code size reduction in embedded processors. SoCC (2016)
Po-Hao Wang, Wei-Chung Cheng, Yung-Hui Yu, Tang-Chieh Kao, Chi-Lun Tsai, Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen
Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations. IEEE Trans. Circuits Syst. II Express Briefs (10) (2016)
Hsuan-Ming Chou, Yi-Chiao Chen, Keng-Hao Yang, Jean Tsao, Shih-Chieh Chang, Wen-Ben Jone, Tien-Fu Chen
High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Protocols. IEEE Trans. Very Large Scale Integr. Syst. 24 (3) (2016)
Win-San Khwa, Meng-Fan Chang, Jau-Yi Wu, Ming-Hsiu Lee, Tzu-Hsiang Su, Keng-Hao Yang, Tien-Fu Chen, Tien-Yen Wang, Hsiang-Pang Li, Matthew BrightSky, SangBum Kim, Hsiang-Lam Lung, Chung Lam
7.3 A resistance-drift compensation scheme to reduce MLC PCM raw BER by over 100× for storage-class memory applications. ISSCC (2016)
Chien-Chen Lin, Jui-Yu Hung, Wen-Zhang Lin, Chieh-Pu Lo, Yen-Ning Chiang, Hsiang-Jen Tsai, Geng-Hau Yang, Ya-Chin King, Chrong Jung Lin, Tien-Fu Chen, Meng-Fan Chang
7.4 A 256b-wordlength ReRAM-based TCAM with 1ns search-time and 14× improvement in wordlength-energyefficiency-density product using 2.5T1R cell. ISSCC (2016)
Po-Hao Wang, Shang-Jen Tsai, Rizal Tanjung, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen
Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors. Integr. 54 (2016)
Meng-Fan Chang, Li-Yue Huang, Wen-Zhang Lin, Yen-Ning Chiang, Chia-Chen Kuo, Ching-Hao Chuang, Keng-Hao Yang, Hsiang-Jen Tsai, Tien-Fu Chen, Shyh-Shyuan Sheu
A ReRAM-Based 4T2R Nonvolatile TCAM Using RC-Filtered Stress-Decoupled Scheme for Frequent-OFF Instant-ON Search Engines Used in IoT and Big-Data Processing. IEEE J. Solid State Circuits 51 (11) (2016)
Yung-Hui Yu, Po-Hao Wang, Shang-Jen Tsai, Tien-Fu Chen
A latency-elastic and fault-tolerant cache for improving performance and reliability on low voltage operation. VLSI-DAT (2015)
Hsuan-Ming Chou, Ming-Yi Hsiao, Yi-Chiao Chen, Keng-Hao Yang, Jean Tsao, Chiao-Ling Lung, Shih-Chieh Chang, Wen-Ben Jone, Tien-Fu Chen
Soft-Error-Tolerant Design Methodology for Balancing Performance, Power, and Reliability. IEEE Trans. Very Large Scale Integr. Syst. 23 (9) (2015)
Hong-Yi Wu, Chien-Chih Chen, Hsiang-Jen Tsai, Yin-Chi Peng, Tien-Fu Chen
Lifetime-aware LRU promotion policy for last-level cache. VLSI-DAT (2015)
Chia-Jung Chang, Yin-Chi Peng, Chien-Chih Chen, Tien-Fu Chen, Pen-Chung Yew
Adaptive granularity and coordinated management for timely prefetching in multi-core systems. VLSI-DAT (2015)
Pei-Yuan Chou, I-Chen Wu, Jai-Wei Lin, Xuan-Yu Lin, Tien-Fu Chen, Tay-Jyi Lin, Jinn-Shyan Wang
Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches. ASICON (2015)
Hsiang-Jen Tsai, Keng-Hao Yang, Yin-Chi Peng, Chien-Chen Lin, Ya-Han Tsao, Meng-Fan Chang, Tien-Fu Chen
Energy-efficient non-volatile TCAM search engine design using priority-decision in memory technology for DPI. DAC (2015)
Meng-Fan Chang, Chien-Chen Lin, Albert Lee, Chia-Chen Kuo, Geng-Hau Yang, Hsiang-Jen Tsai, Tien-Fu Chen, Shyh-Shyuan Sheu, Pei-Ling Tseng, Heng-Yuan Lee, Tzu-Kun Ku
17.5 A 3T1R nonvolatile TCAM using MLC ReRAM with Sub-1ns search time. ISSCC (2015)
Li-Yue Huang, Meng-Fan Chang, Ching-Hao Chuang, Chia-Chen Kuo, Chien-Fu Chen, Geng-Hau Yang, Hsiang-Jen Tsai, Tien-Fu Chen, Shyh-Shyuan Sheu, Keng-Li Su, Frederick T. Chen, Tzu-Kun Ku, Ming-Jinn Tsai, Ming-Jer Kao
ReRAM-based 4T2R nonvolatile TCAM with 7x NVM-stress reduction, and 4x improvement in speed-wordlength-capacity for normally-off instant-on filter-based search engines used in big-data processing. VLSIC (2014)
Hsiang-Jen Tsai, Chien-Chih Chen, Keng-Hao Yang, Ting-Chin Yang, Li-Yue Huang, Ching-Hao Chuang, Meng-Fan Chang, Tien-Fu Chen
Leveraging Data Lifetime for Energy-Aware Last Level Non-Volatile SRAM Caches using Redundant Store Elimination. DAC (2014)
Tzu-Hsiang Su, Hsiang-Jen Tsai, Keng-Hao Yang, Po-Chun Chang, Tien-Fu Chen, Yi-Ting Zhao
Reconfigurable vertical profiling framework for the android runtime system. ACM Trans. Embed. Comput. Syst. 13 (2s) (2014)
Chien-Chih Chen, Yin-Chi Peng, Cheng-Fen Chen, Wei-Shan Wu, Qinghao Min, Pen-Chung Yew, Weihua Zhang, Tien-Fu Chen
DAPs: Dynamic Adjustment and Partial Sampling for Multithreaded/Multicore Simulation. DAC (2014)
Po-Hao Wang, Wei-Chung Cheng, Yung-Hui Yu, Tang-Chieh Kao, Chi-Lun Tsai, Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen
Variation-aware and adaptive-latency accesses for reliable low voltage caches. VLSI-SoC (2013)
Yin-Chi Peng, Chien-Chih Chen, Chia-Jung Chang, Tien-Fu Chen, Pen-Chung Yew
Cross-layer dynamic prefetching allocation strategies for high-performance multicores. VLSI-DAT (2013)
Shing-Yu Chen, Ming-Yi Hsiao, Wen-Ben Jone, Tien-Fu Chen
A configurable bus-tracer for error reproduction in post-silicon validation. VLSI-DAT (2013)
Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, Ting-Yu Shyu, Chien-Yung Chou, Shien-Chun Luo, Jiun-In Guo, Tien-Fu Chen, Gene C. H. Chuang, Yuan-Hua Chu, Liang-Chia Cheng, Hong-Men Su, Chewnpu Jou, Meikei Ieong, Cheng-Wen Wu, Jinn-Shyan Wang
A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. ISSCC (2013)
Chieh-Jen Cheng, Chao-Ching Wang, Wei-Chun Ku, Tien-Fu Chen, Jinn-Shyan Wang
A Scalable High-Performance Virus Detection Processor Against a Large Pattern Set for Embedded Network Security. IEEE Trans. Very Large Scale Integr. Syst. 20 (5) (2012)
Shing-Yu Chen, Chi-Neng Wen, Geng-Hau Yang, Wen-Ben Jone, Tien-Fu Chen
IMITATOR: A deterministic multicore replay system with refining techniques. VLSI-DAT (2012)
Chi-Neng Wen, Shu-Hsuan Chou, Chien-Chih Chen, Tien-Fu Chen
NUDA: A Non-Uniform Debugging Architecture and Nonintrusive Race Detection for Many-Core Systems. IEEE Trans. Computers 61 (2) (2012)
Shu-Hsuan Chou, Chien-Chih Chen, Chi-Neng Wen, Tien-Fu Chen, Tay-Jyi Lin
Hierarchical circuit-switched NoC for multicore video processing. Microprocess. Microsystems 35 (2) (2011)
Yung-Cheng Ma, Chung-Ping Chung, Tien-Fu Chen
Load and storage balanced posting file partitioning for parallel information retrieval. J. Syst. Softw. 84 (5) (2011)
Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh
Maintaining performance on power gating of microprocessor functional units by using a predictive pre-wakeup strategy. ACM Trans. Archit. Code Optim. 8 (3) (2011)
Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh
Adaptive Pipeline voltage Scaling in High Performance Microprocessor. J. Circuits Syst. Comput. 19 (8) (2010)
Chi-Neng Wen, Shu-Hsuan Chou, Tien-Fu Chen, Tay-Jyi Lin
RunAssert: A non-intrusive run-time assertion for parallel programs debugging. DATE (2010)
Chi-Neng Wen, Shu-Hsuan Chou, Tien-Fu Chen, Alan Peisheng Su
NUDA: a non-uniform debugging architecture and non-intrusive race detection for many-core. DAC (2009)
Shu-Hsuan Chou, Chi-Neng Wen, Yan-Ling Liu, Tien-Fu Chen
VeriC: A semi-hardware description language to bridge the gap between ESL design and RTL models. ISQED (2009)
Wei-Chun Ku, Shu-Hsuan Chou, Jui-Chin Chu, Chi-Lin Liu, Tien-Fu Chen, Jiun-In Guo, Jinn-Shyan Wang
VisoMT: A Collaborative Multithreading Multicore Processor for Multimedia Applications With a Fast Data Switching Mechanism. IEEE Trans. Circuits Syst. Video Technol. 19 (11) (2009)
Shu-Hsuan Chou, Chien-Chih Chen, Chi-Neng Wen, Yi-Chao Chan, Tien-Fu Chen, Chao-Ching Wang, Jinn-Shyan Wang
No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips. DAC (2009)
Chao-Ching Wang, Chieh-Jen Cheng, Tien-Fu Chen, Jinn-Shyan Wang
An Adaptively Dividable Dual-Port BiTCAM for Virus-Detection Processors in Mobile Devices. IEEE J. Solid State Circuits 44 (5) (2009)
Chi-Neng Wen, Shu-Hsuan Chou, Tien-Fu Chen
dIP: A Non-intrusive Debugging IP for Dynamic Data Race Detection in Many-Core. ISPAN (2009)
Chao-Ching Wang, Chieh-Jen Cheng, Tien-Fu Chen, Jinn-Shyan Wang
An Adaptively Dividable Dual-Port BiTCAM for Virus-Detection Processors in Mobile Devices. ISSCC (2008)
Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
Tailoring circuit-switched network-on-chip to application-specific system-on-chip by two optimization schemes. ACM Trans. Design Autom. Electr. Syst. 13 (1) (2008)
Jui-Chin Chu, Wei-Chun Ku, Shu-Hsuan Chou, Tien-Fu Chen, Jiun-In Guo
An Embedded Coherent-Multithreading Multimedia Processor and Its Programming Model. DAC (2007)
Kuei-Chung Chang, Tien-Fu Chen
Efficient segment-based video transcoding proxy for mobile multimedia services. J. Syst. Archit. 53 (11) (2007)
Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh
Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling. HiPEAC (2007)
Jih-Sheng Shen, Kuei-Chung Chang, Tien-Fu Chen
On a design of crossroad switches for low-power on-chip communication architectures. ISCAS (2006)
Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs. DAC (2006)
Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
Fast Run-Time Power Monitoring Methodology for Embedded Systems. ESA (2006)
Jui-Chin Chu, Chih-Wen Huang, He-Chun Chen, Keng-Po Lu, Ming-Shuan Lee, Jiun-In Guo, Tien-Fu Chen
Design of customized functional units for the VLIW-based multi-threading processor core targeted at multimedia applications. ISCAS (2006)
Wei-Chun Ku, Shu-Hsuan Chou, Jui-Chin Chu, Chih-Heng Kang, Tien-Fu Chen, Jiun-In Guo
Collaborative Multithreading: An Open Scalable Processor Architecture for Embedded Multimedia Applications. ICME (2006)
Kuei-Chung Chang, Tien-Fu Chen, Wei-Yen Chuang
System-Level Power-Aware Scheduling by Operation-based Prediction. PSC (2005)
Chih-wen Hsueh, Tien-Fu Chen, Rong-Guey Chang, Shi-Wu Lo
Development of Architecture and Software Technologies in High-Performance Low-Power SoC Design. RTCSA (2005)
Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
Crossroad System-on-Chip Communication Architecture for Low Power Embedded Systems. ESA (2005)
Tien-Fu Chen, Chia-Ming Hsu, S.-R. Wu
Flexible Heterogeneous Multicore Architectures for Versatile Media Processing Via Customized Long Instruction Words. IEEE Trans. Circuits Syst. Video Technol. 15 (5) (2005)
Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
A low-power crossroad switch architecture and its core placement for network-on-chip. ISLPED (2005)
Kuei-Chung Chang, Ren-Yo Wu, Tien-Fu Chen
Efficient Segment-Based Video Transcoding Proxy for Mobile Multimedia Services. ICME (2005)
Jinn-Shyan Wang, Hung-Yu Li, Chingwei Yeh, Tien-Fu Chen
Design techniques for single-low-V/sub DD/ CMOS systems. IEEE J. Solid State Circuits 40 (5) (2005)
Rei-Chin Ju, Jia-Wei Chen, Jiun-In Guo, Tien-Fu Chen
A parameterized power-aware IP core generator for the 2-D 8×8 DCT/IDCT. ISCAS (2) (2004)
Tien-Fu Chen, Tsung-Ming Hsieh, Chun-Li Wei
Unified bus encoding by stream reconstruction with variable strides. ISCAS (2) (2004)
Hao-Ran Liu, Tien-Fu Chen
Scalable locality-aware event dispatching mechanism for network servers. IEE Proc. Softw. 151 (3) (2004)
Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Tien-Fu Chen
A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms. ISCAS (2) (2004)
Yung-Cheng Ma, Tien-Fu Chen, Chung-Ping Chung
Branch-and-bound task allocation with task clustering-based pruning. J. Parallel Distributed Comput. 64 (11) (2004)
Chih-Da Chien, Chien-Chang Lin, Jiun-In Guo, Tien-Fu Chen
A power-aware IP core generator for the one-dimensional discrete Fourier transform. ISCAS (3) (2004)
Hung-Cheng Wu, Tien-Fu Chen, Hung-Yu Li, Jinn-Shyan Wang
Energy Efficient Caching-on-Cache Architectures for Embedded Systems. J. Inf. Sci. Eng. 19 (5) (2003)
Wann-Yun Shieh, Tien-Fu Chen, Chung-Ping Chung
A Tree-Based inverted File for Fast Ranked-Document Retrieval. IKE (2003)
Yung-Cheng Ma, Jih-Ching Chiu, Tien-Fu Chen, Chung-Ping Chung
Variable-size data item placement for load and storage balancing. J. Syst. Softw. 66 (2) (2003)
Chia-Ming Hsu, Tien-Fu Chen
Flexible Heterogeneous Multicore Architectures for Media Processing via Customized Long Instruction Words. VLSI-SOC (2003)
Hao-Ran Liu, Tien-Fu Chen
A Scalable Locality-Aware Event Dispatching Mechanism for Network Servers. WWW (Posters) (2003)
Wann-Yun Shieh, Tien-Fu Chen, Jean Jyh-Jiun Shann, Chung-Ping Chung
Inverted file compression through document identifier reassignment. Inf. Process. Manag. 39 (1) (2003)
Yung-Cheng Ma, Tien-Fu Chen, Chung-Ping Chung
Posting file partitioning and parallel information retrieval. J. Syst. Softw. 63 (2) (2002)
Jian-Liang Kuo, Tien-Fu Chen
Dynamic voltage leveling scheduling for real-time embedded systems on low-power variable speed processors. CASES (2002)
Tien-Fu Chen, Yi-Min Hwang
Decoupling of data and tag arrays for on-chip caches. Microprocess. Microsystems 25 (9-10) (2002)
Chung-Hung Lai, Tien-Fu Chen
Compressing inverted files in scalable information systems by binary decision diagram encoding . SC (2001)
Chi-Min Lin, Tien-Fu Chen
Dynamic memory management for real-time embedded Java chips. RTCSA (2000)
J.-Y. Chen, Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, Tien-Fu Chen
Segmented bus design for low-power systems. IEEE Trans. Very Large Scale Integr. Syst. 7 (1) (1999)
Jung-Long Jiang, Tien-Fu Chen
SBA: a server-initiated playback scheme supporting variable bit rate control. IEEE Trans. Consumer Electron. 45 (1) (1999)
Tien-Fu Chen
Supporting Highly-Speculative Execution via Adaptive Branch Trees. HPCA (1998)
Tien-Fu Chen
Reducing memory penalty by a programmable prefetch engine for on-chip caches. Microprocess. Microsystems 21 (2) (1997)
Tien-Fu Chen
Techniques for The Efficient Analysis of Cache Performance. J. Inf. Sci. Eng. 12 (4) (1996)
Tien-Fu Chen
Efficient trace-sampling simulation techniques for cache performance analysis. Annual Simulation Symposium (1996)
Tien-Fu Chen, Jean-Loup Baer
Effective Hardware Based Data Prefetching for High-Performance Processors. IEEE Trans. Computers 44 (5) (1995)
Tien-Fu Chen
An effective programmable prefetch engine for on-chip caches. MICRO (1995)
Tien-Fu Chen, Jean-Loup Baer
A Performance Study of Software and Hardware Data Prefetching Schemes. ISCA (1994)
Jean-Loup Baer, Tien-Fu Chen
An Evaluation of Hardware and Software Data Prefetching. Applications in Parallel and Distributed Computing (1994)
Tien-Fu Chen, Jean-Loup Baer
Reducing Memory Latency via Non-blocking and Prefetching Caches. ASPLOS (1992)
Jean-Loup Baer, Tien-Fu Chen
An effective on-chip preloading scheme to reduce data access penalty. SC (1991)