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VeriC: A semi-hardware description language to bridge the gap between ESL design and RTL models.
Shu-Hsuan Chou
Chi-Neng Wen
Yan-Ling Liu
Tien-Fu Chen
Published in:
ISQED (2009)
Keyphrases
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hardware description language
integrated circuit
hardware design
probabilistic model
design process
machine learning
statistical models
metamodel
modelling language
programmable logic
bayesian networks
pairwise
statistically significant
language learning