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7.3 A resistance-drift compensation scheme to reduce MLC PCM raw BER by over 100× for storage-class memory applications.

Win-San KhwaMeng-Fan ChangJau-Yi WuMing-Hsiu LeeTzu-Hsiang SuKeng-Hao YangTien-Fu ChenTien-Yen WangHsiang-Pang LiMatthew BrightSkySangBum KimHsiang-Lam LungChung Lam
Published in: ISSCC (2016)
Keyphrases
  • garbage collection
  • computational complexity
  • error rate
  • error accumulation
  • memory requirements
  • data storage
  • random access
  • virtual memory
  • memory capacity
  • multi label
  • memory management
  • channel capacity