Yung-Chen Chien

Publication Activity (10 Years)

Years Active: 2011-2018
Publications (10 Years): 2

Top Topics

Cache Management

Semantic Caching

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Multi Scale Comput. Syst.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Yung-Chen Chien, Jinn-Shyan Wang
A 0.2 V 32-Kb 10T SRAM With 41 nW Standby Power for IoT Applications. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2018)
Po-Hao Wang, Yung-Chen Chien, Shang-Jen Tsai, Xuan-Yu Lin, Rizal Tanjung, Yi-Sian Lin, Shu-Wei Syu, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen
ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures. IEEE Trans. Very Large Scale Integr. Syst. 25 (12) (2017)
Jinn-Shyan Wang, Yung-Chen Chien, Fengzhi Liu, Pei-Yao Chang
A Calibration-Free PVTD-Variation-Tolerant Sensing Scheme for Footless-8T SRAM Designs. IEEE Trans. Multi Scale Comput. Syst. 1 (3) (2015)
Jinn-Shyan Wang, Yung-Chen Chien, Jia-Hong Lin, Chun-Yuan Cheng, Ying-Ting Ma, Chung-Hsun Huang
ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designs. ASICON (2011)