Jih-Ching Chiu

Publication Activity (10 Years)

Years Active: 1997-2022
Publications (10 Years): 10

Top Topics

Design Requirements

Routing Algorithm

Embedded Systems

Top Venues

Comput. Electr. Eng.

IEEE Trans. Broadcast.

Publications

Jih-Ching Chiu, Yan-Ting Wu, Yung-Chi Liu, Chi-Yang Hsieh
Design and Implementation of the Link-List DMA Controller for High Bandwidth Data Streaming. ICS (2022)
Jih-Ching Chiu, Zhe-You Yan, Yung-Chi Liu
Design and Implementation of the CNN Accelator Based on Multi-streaming SIMD Mechanisms. ICS (2022)
Jih-Ching Chiu, Yu-Quen Chen, Yi-Xiang Wang, Yung-Chi Liu
Design and Implementation of the Optimized Computing Architecture for Matrix Decomposition Algorithms. ICS (2022)
Jih-Ching Chiu, Yu-Yi Wang, Wei-Yi Lin
The Brain Memory Architecture HW/SW Co-Design Platform with Adaptive CNN Algorithm. ICS (2020)
Jih-Ching Chiu, Hao-Yu Tseng, Zhi-Yu Lee
Design of Multidimension-media Streaming Protocol Based on RTSP. ICS (2020)
Jih-Ching Chiu, Cheng-Lin Tsai, Zhi-Yu Lee
Design and Implement Adaptive Tree Topology Mechanism For Wi-Fi Wireless Network. ICS (2020)
Jih-Ching Chiu, Jun-Jiang Chen, Kuan-Lun Su
Design and Implement Robust Wireless Network Based on TCP Protocol. ICS (2020)
Tsung-Lin Lee, Jih-Ching Chiu, Yueh-Lin Li
Adaptive Linked-List Mechanism for Wi-Fi Wireless Network. ICS (2018)
Guan-Jen Huang, Jih-Ching Chiu, Yueh-Lin Li
Design and Implementation of Tree Topology Algorithm for Power Line Communication Network. ICS (2018)
Yi-Xuan Lu, Jih-Ching Chiu, Shu-Jung Chao, Yong-Bin Ye
Design of Instruction Analyzer with Semantic-Based Loop Unrolling Mechanism in the Hyperscalar Architecture. ICS (2018)
Jih-Ching Chiu, Chun-Yao Zheng, Yao-Chin Huang, Kai-Ming Yang
Design and implementation of sequential repair and backup routing protocol for wireless mesh network. ICNC (2014)
Jih-Ching Chiu, Wen-Shin Wang, Chien-Lung Chen
Linked List Routing Algorithm with Wormhole Mechanism for Data Collecting Wireless Network. ICS (2014)
Jih-Ching Chiu, Kai-Ming Yang, Yu-Liang Chou, Chih-Kang Wu
A relation-exchanging buffering mechanism for instruction and data streaming. Comput. Electr. Eng. 39 (4) (2013)
Hsuan-Chang Lee, Jih-Ching Chiu, Ken-Huang Lin
Two-Dimensional Interpolation-Assisted Channel Prediction for OFDM Systems. IEEE Trans. Broadcast. 59 (4) (2013)
Jih-Ching Chiu, Kai-Ming Yang
High-speed low-power multiplexer-based selector for priority policy. Comput. Electr. Eng. 39 (2) (2013)
Jih-Ching Chiu, Kai-Ming Yang, Yu-Liang Chou
A hyperscalar dual-core architecture for embedded systems. Microprocess. Microsystems 37 (8-B) (2013)
Jih-Ching Chiu, Kai-Ming Yang, Chen-Ang Wong
Analytical Modeling for Multi-transaction Bus on Distributed Systems. ICA3PP (2) (2012)
Jih-Ching Chiu, Yu-Liang Chou, Po-Kai Chen, Ding-Siang Su
A Unitable Computing Architecture for Chip Multiprocessors. Comput. J. 54 (12) (2011)
Jih-Ching Chiu, Yu-Liang Chou, Tseng-Kuei Lin
The Basic Block Reassembling Instruction Stream Buffer with LWBTB for X86 ISA. J. Inf. Sci. Eng. 26 (4) (2010)
Jih-Ching Chiu, Yu-Liang Chou
A multi-streaming SIMD multimedia computing engine. Microprocess. Microsystems 34 (7-8) (2010)
Jih-Ching Chiu, Kai-Ming Yang
A Novel instruction stream buffer for VLIW architectures. Comput. Electr. Eng. 36 (1) (2010)
Jih-Ching Chiu, Yu-Liang Chou, Po-Kai Chen
Hyperscalar: A Novel Dynamically Reconfigurable Multi-core Architecture. ICPP (2010)
Jih-Ching Chiu, Yu-Liang Chou, Ding-Siang Su
A hyperscalar multi-core architecture. Conf. Computing Frontiers (2010)
Jih-Ching Chiu, Ta-Li Yeh
IRES: An integrated software and hardware interface framework for reconfigurable embedded system. IET Comput. Digit. Tech. 4 (1) (2010)
Jih-Ching Chiu, Ta-Li Yeh, Mun-Kit Leong
The Software and Hardware Integration Linker for Reconfigurable Embedded System. CSE (2) (2009)
Jih-Ching Chiu, Kai-Ming Yang, Mu-Chi Chang
The Rendezvous Mechanism for the Multi-core AMBA System. ICPP Workshops (2009)
Jih-Ching Chiu, Yu-Liang Chou, Hua-Yi Tzeng
A multi-streaming SIMD architecture for multimedia applications. Conf. Computing Frontiers (2009)
Jih-Ching Chiu, Kai-Ming Yang, Yu-Liang Chou
Design of a novel SIMD architecture by fusing operations and registers. ICS (2009)
Jih-Ching Chiu, Yu-Liang Chou, Ta-Li Yeh, Tseng-Kuei Lin
Designs of the basic block reassembling Instruction Stream Buffer for X86 ISA. ACSAC (2008)
Jih-Ching Chiu, Yu-Liang Chou, Ren-Bang Lin
The Multi-context Reconfigurable Processing Unit for Fine-grain Computing. J. Inf. Sci. Eng. 24 (3) (2008)
Jih-Ching Chiu, Ren-Bang Lin
FMRPU: Design of Fine-Grain Multi-context Reconfigurable Processing Unit. Asia-Pacific Computer Systems Architecture Conference (2005)
Yung-Cheng Ma, Jih-Ching Chiu, Tien-Fu Chen, Chung-Ping Chung
Variable-size data item placement for load and storage balancing. J. Syst. Softw. 66 (2) (2003)
Jih-Ching Chiu, Michael Jin-Yi Wang, Chung-Ping Chung
Design of Instruction Address Queue for High Degree X86 Superscalar Architecture. J. Inf. Sci. Eng. 18 (3) (2002)
Jih-Ching Chiu, I-Huan Huang, Chung-Ping Chung
Design of Instruction Stream Buffer with Trace Support for X86 Processors. ICCD (2000)
Shyh-An Chi, R.-Ming Shiu, Jih-Ching Chiu, Si-En Chang, Chung-Ping Chung
Instruction Cache Prefetching with Extended BTB. ICPADS (1997)