Chung-Ping Chung

Publication Activity (10 Years)

Years Active: 1989-2015
Publications (10 Years): 0

Top Topics

Video Communication

Deblocking Filter

Top Venues

J. Inf. Sci. Eng.

ACM Trans. Embed. Comput. Syst.

Future Gener. Comput. Syst.

Publications

I-Wei Wu, Jean Jyh-Jiun Shann, Chung-Ping Chung
Reconfigurable Custom Functional Unit Generation and Exploitation for Multiple-Issue Processors. J. Inf. Sci. Eng. 31 (4) (2015)
Tsung-Hsi Weng, Chung-Ping Chung
Exploiting fine-grain parallelism in the H.264 deblocking filter by operation reordering. Future Gener. Comput. Syst. 37 (2014)
I-Wei Wu, Jean Jyh-Jiun Shann, Wei-Chung Hsu, Chung-Ping Chung
Extended Instruction Exploration for Multiple-Issue Architectures. ACM Trans. Embed. Comput. Syst. 13 (4) (2014)
Tsung-Hsi Weng, Yi-Ting Wang, Chung-Ping Chung
Exploiting Parallelism in the H.264 Deblocking Filter by Operation Reordering. ICA3PP (1) (2011)
I-Wei Wu, Chung-Ping Chung, Jean Jyh-Jiun Shann
Area-Efficient Instruction Set Extension Exploration with Hardware Design Space Exploration. J. Inf. Sci. Eng. 27 (5) (2011)
Peter Deayton, Chung-Ping Chung
Set Utilization Based Dynamic Shared Cache Partitioning. ICPADS (2011)
Walter Yuan-Hwa Li, Chin-Ling Huang, Chung-Ping Chung
Tolerating Load Miss-Latency by Extending Effective Instruction Window with Low Complexity. ICPP (2011)
Yung-Cheng Ma, Chung-Ping Chung, Tien-Fu Chen
Load and storage balanced posting file partitioning for parallel information retrieval. J. Syst. Softw. 84 (5) (2011)
Hui-Shan Wang, I-Wei Wu, Jean Jyh-Jiun Shann, Chung-Ping Chung
Reconfigurable custom functional unit generation and exploitation in multiple-issue processors. SASP (2010)
Chung-Ping Chung, Tung-Lin Lu, Hui-Chin Yang
H-Buffer: An Efficient History-Based and Overflow Sharing Transparent Fragment Storage Method. CSE (2) (2009)
Oluwayomi B. Adamo, Afrin Naz, Tommy Janjusic, Krishna M. Kavi, Chung-Ping Chung
Smaller Split L-1 Data Caches for Multi-core Processing Systems. ISPAN (2009)
Yi-Chi Chen, Hui-Chin Yang, Chung-Ping Chung, Wei-Ting Wang
Dynamic Reconfigurable Shaders with Load Balancing for Embedded Graphics Processing. CSE (2) (2009)
Hsiu-ching Hsieh, Chih-Chieh Hsiao, Hui-Chin Yang, Chung-Ping Chung, Jean Jyh-Jiun Shann
Methods for Precise False-Overlap Detection in Tile-Based Rendering. CSE (2) (2009)
Chung-Ping Chung, Hong-Wei Chen, Hui-Chin Yang
Blocked-Z Test for Reducing Rasterization, Z Test and Shading Workloads. CSE (2) (2009)
Chih-Chieh Hsiao, Chung-Ping Chung, Hui-Chin Yang
A Hierarchical Primitive Lists Structure for Tile-Based Rendering. CSE (2) (2009)
Wei-Hau Chiao, Chung-Ping Chung
Filtering of Unnecessary Branch Predictor Lookups for Low-power Processor Architecture. J. Inf. Sci. Eng. 24 (4) (2008)
Guan-Ying Chiu, Hui-Chin Yang, Walter Yuan-Hwa Li, Chung-Ping Chung
Mechanism for return stack and branch history corrections under misprediction in deep pipeline design. ACSAC (2008)
I-Wei Wu, Zhiyuan Chen, Jean Jyh-Jiun Shann, Chung-Ping Chung
Instruction Set Extension Exploration in Multiple-Issue Architecture. DATE (2008)
Shun-Chieh Chang, W. Y. Li, Yuan-Jung Kuo, Chung-Ping Chung
Early load: Hiding load latency in deep pipeline processor. ACSAC (2008)
Po-Chun Chang, I-Wei Wu, Jean Jyh-Jiun Shann, Chung-Ping Chung
ETAHM: an energy-aware task allocation algorithm for heterogeneous multiprocessor. DAC (2008)
Hui-Chin Yang, Li-Ming Wang, Chung-Ping Chung
iAIM: An Intelligent Autonomous Instruction Memory with Branch Handling Capability. ICYCS (2008)
I-Wei Wu, Shih-Chia Huang, Chung-Ping Chung, Jean Jyh-Jiun Shann
Instruction Set Extension Generation with Considering Physical Constraints. HiPEAC (2007)
Wei-Ting Wang, Yi-Chi Chen, Chung-Ping Chung
A Run-Time Reconfigurable Fabric for 3D Texture Filtering. ASAP (2007)
Wei-Ting Wang, Wai-Hong Tam, Yi-Chi Chen, Kuen-Cheng Chiang, Chung-Ping Chung
Selecting Heterogeneous Computation Blocks for Reconfigurable JPEG Codec Computing. ERSA (2007)
Hui-Chin Yang, Chung-Ping Chung
Autonomous Instruction Memory Equipped with Dynamic Branch Handling Capability. CDES (2006)
Bin-Hua Tein, I-Wei Wu, Chung-Ping Chung
Instruction Fetch Energy Reduction Using Forward-Branch Bufferable Innermost Loop Buffer. CDES (2006)
Cher-Sheng Cheng, Jean Jyh-Jiun Shann, Chung-Ping Chung
Unique-order interpolative coding for fast querying and space-efficient indexing in information retrieval systems. Inf. Process. Manag. 42 (2) (2006)
Cher-Sheng Cheng, Chung-Ping Chung, Jean Jyh-Jiun Shann
Fast query evaluation through document identifier assignment for inverted file-based information retrieval systems. Inf. Process. Manag. 42 (3) (2006)
Wann-Yun Shieh, Chung-Ping Chung
A statistics-based approach to incrementally update inverted files. Inf. Process. Manag. 41 (2) (2005)
Ching-Wen Chen, Chung-Ping Chung
Designing A Disjoint Paths Interconnection Network with Fault Tolerance and Collision Solving. J. Supercomput. 34 (1) (2005)
Wei-Hao Chiao, Tsung-Hsi Weng, Jean Jyh-Jiun Shann, Chung-Ping Chung, Jimmy Lu
Low-Power Data Address Bus Encoding Method. CDES (2005)
Yau-Chong Hu, Wei-Hau Chiao, Jean Jyh-Jiun Shann, Chung-Ping Chung, Wen-Feng Chen
Low-Power Branch Prediction. CDES (2005)
Cher-Sheng Cheng, Jean Jyh-Jiun Shann, Chung-Ping Chung
A Unique-Order Interpolative Code for Fast Querying and Space-Efficient Indexing in Information Retrieval Systems. ITCC (2) (2004)
Lee-Ren Ton, Lung-Chung Chang, Jean Jyh-Jiun Shann, Chung-Ping Chung
A software/hardware cooperated stack operations folding model for Java processors. J. Syst. Softw. 72 (3) (2004)
Yung-Cheng Ma, Tien-Fu Chen, Chung-Ping Chung
Branch-and-bound task allocation with task clustering-based pruning. J. Parallel Distributed Comput. 64 (11) (2004)
Kelvin Lin, Jean Jyh-Jiun Shann, Chung-Ping Chung
Code compression by register operand dependency. J. Syst. Softw. 72 (3) (2004)
Wann-Yun Shieh, Chung-Ping Chung
A Statistics-Based Approach to Incrementally Update Inverted Files. IKE (2003)
Wann-Yun Shieh, Tien-Fu Chen, Chung-Ping Chung
A Tree-Based inverted File for Fast Ranked-Document Retrieval. IKE (2003)
Yung-Cheng Ma, Jih-Ching Chiu, Tien-Fu Chen, Chung-Ping Chung
Variable-size data item placement for load and storage balancing. J. Syst. Softw. 66 (2) (2003)
Wann-Yun Shieh, Tien-Fu Chen, Jean Jyh-Jiun Shann, Chung-Ping Chung
Inverted file compression through document identifier reassignment. Inf. Process. Manag. 39 (1) (2003)
Ching-Wen Chen, Neng-Pin Lu, Chung-Ping Chung
3-Disjoint gamma interconnection networks. J. Syst. Softw. 66 (2) (2003)
Kelvin Lin, Chung-Ping Chung, Jean Jyh-Jiun Shann
Compressing MIPS code by multiple operand dependencies. ACM Trans. Embed. Comput. Syst. 2 (4) (2003)
Wann-Yun Shieh, Jean Jyh-Jiun Shann, Chung-Ping Chung
An Inverted File Cache for Fast Information Retrieval. J. Inf. Sci. Eng. 19 (4) (2003)
Kelvin Lin, Jean Jyh-Jiun Shann, Chung-Ping Chung
Code Compression by Register Operand Dependency. Interaction between Compilers and Computer Architectures (2002)
Lee-Ren Ton, Lung-Chung Chang, Jean Jyh-Jiun Shann, Chung-Ping Chung
Design of an optimal folding mechanism for Java processors. Microprocess. Microsystems 26 (8) (2002)
Yung-Cheng Ma, Tien-Fu Chen, Chung-Ping Chung
Posting file partitioning and parallel information retrieval. J. Syst. Softw. 63 (2) (2002)
Jih-Ching Chiu, Michael Jin-Yi Wang, Chung-Ping Chung
Design of Instruction Address Queue for High Degree X86 Superscalar Architecture. J. Inf. Sci. Eng. 18 (3) (2002)
Lee-Ren Ton, Lung-Chung Chang, Chung-Ping Chung
An analytical POC stack operations folding for continuous and discontinuous Java bytecodes. J. Syst. Archit. 48 (1-3) (2002)
Ching-Wen Chen, Chung-Ping Chung
Fault-tolerant gamma interconnection network without backtracking. J. Syst. Softw. 58 (1) (2001)
Yung-Cheng Ma, Chung-Ping Chung
A dominance relation enhanced branch-and-bound task allocation. J. Syst. Softw. 58 (2) (2001)
R.-Ming Shiu, Neng-Pin Lu, Chung-Ping Chung
Applying stack simulation for branch target buffers. J. Syst. Softw. 52 (1) (2000)
Lee-Ren Ton, Lung-Chung Chang, Chung-Ping Chung
Exploiting Java Bytecode Parallelism by Enhanced POC Folding Model (Research Note). Euro-Par (2000)
Jih-Ching Chiu, I-Huan Huang, Chung-Ping Chung
Design of Instruction Stream Buffer with Trace Support for X86 Processors. ICCD (2000)
Ruey-Liang Ma, Chung-Ping Chung
Reducing Memory Traffic and Accelerting Prolog Execution in a Superscalar Prolog System. J. Inf. Sci. Eng. 15 (6) (1999)
Lee-Ren Ton, Lung-Chung Chang, Min-Fu Kao, Han-Min Tseng, Shi-Sheng Shang, Ruey-Liang Ma, Dze-Chaung Wang, Chung-Ping Chung
Instruction Folding in Java Processor. ICPADS (1997)
Shyh-An Chi, R.-Ming Shiu, Jih-Ching Chiu, Si-En Chang, Chung-Ping Chung
Instruction Cache Prefetching with Extended BTB. ICPADS (1997)
Neng-Pin Lu, Chung-Ping Chung
A Fault-Tolerant Multistage Combining Network. J. Parallel Distributed Comput. 34 (1) (1996)
Chang-Chung Liu, R.-Ming Shiu, Chung-Ping Chung
Register renaming for x86 superscalar design. ICPADS (1996)
Ren-Lianq Cheng, Chung-Ping Chung
An Approximate Agreement Algorithm for Wraparound Meshes. Int. J. High Speed Comput. 7 (3) (1995)
Hong Chich Chou, Chung-Ping Chung
An Optimal Instruction Scheduler for Superscalar Processor. IEEE Trans. Parallel Distributed Syst. 6 (3) (1995)
Neng-Pin Lu, Chung-Ping Chung
Memory System Design in Superscalar Processing. Int. J. High Speed Comput. 7 (3) (1995)
Ruey-Liang Ma, Chung-Ping Chung
Periodic Adaptive Branch Prediction and its Application in Superscalar Processing in Prolog. Comput. J. 38 (6) (1995)
Tang-Show Hwang, Chung-Ping Chung
Delayed Precise Invalidation - A Software Cache Coherence Scheme. ICPADS (1994)
Hong Chich Chou, Chung-Ping Chung
Optimal multiprocessor task scheduling using dominance and equivalence relations. Comput. Oper. Res. 21 (4) (1994)
Yuh-Horng Shiau, Chung-Ping Chung
Effects and Handling of Instruction Class Contention in Superscalar Processing. Int. J. High Speed Comput. 6 (3) (1994)
Ruey-Liang Ma, Chung-Ping Chung
Branch Prediction for Enhancing Fine-Grained Parallelism in Prolog. ICPADS (1994)
Hong Chich Chou, Chung-Ping Chung
Modeling of Superscalar Instruction Scheduling and Analysis of a Heuristic Scheduling Algorithm. BIT 33 (3) (1993)
Ren-Lianq Cheng, Chung-Ping Chung
Reaching Approximate Agreement on Hypercube. Parallel Comput. 19 (7) (1993)
Hong Chich Chou, Chung-Ping Chung
A bound analysis of scheduling instructions on pipelined processors with a maximal delay of one cycle. Parallel Comput. 18 (4) (1992)
Chung-Ping Chung, Wen-Yang Lin
Vectorization of Sorting Algorithms. Int. J. High Speed Comput. 4 (3) (1992)
Yuh-Horng Shiau, Chung-Ping Chung
Adoptability and effectiveness of microcode compaction algorithms in superscalar processing. Parallel Comput. 18 (5) (1992)
Hong Chich Chou, Chung-Ping Chung
Upper Bound Analysis of Scheduling Arbitrary-Delay Instructions on Typed Pipelined Processors. Int. J. High Speed Comput. 4 (4) (1992)
Cheng Chen, Chung-Ping Chung, Cheng-Chin Chiang, Hsin-Chia Fu, S. J. Wang
An Or-Parallel Inference Model Based on Multi RISC-Style Processing System. J. Inf. Sci. Eng. 7 (4) (1991)
Chung-Ping Chung, Shyi-Chyi Jeng, Hong Chich Chou, Cheng Chen
Design of Dual-ALU CRISC and Its Concurrent Execution . J. Inf. Sci. Eng. 5 (3) (1989)