Jean Jyh-Jiun Shann

Publication Activity (10 Years)

Years Active: 1994-2017
Publications (10 Years): 2

Top Topics

Intra Prediction

Instruction Set Architecture

Avc Video Coding

Top Venues

J. Inf. Sci. Eng.

ACM Trans. Embed. Comput. Syst.

Publications

Han-Ping Lo, Jean Jyh-Jiun Shann
Translating OpenACC program for HAS environment. CITS (2017)
Hao-Wei Peng, Jean Jyh-Jiun Shann
Translating OpenACC to LLVM IR with SPIR kernels. ICIS (2016)
I-Wei Wu, Jean Jyh-Jiun Shann, Chung-Ping Chung
Reconfigurable Custom Functional Unit Generation and Exploitation for Multiple-Issue Processors. J. Inf. Sci. Eng. 31 (4) (2015)
I-Chun Liu, I-Wei Wu, Jean Jyh-Jiun Shann
Instruction Emulation and OS Supports of a Hybrid Binary Translator for x86 Instruction Set Architecture. UIC/ATC/ScalCom (2015)
I-Wei Wu, Jean Jyh-Jiun Shann, Wei-Chung Hsu, Chung-Ping Chung
Extended Instruction Exploration for Multiple-Issue Architectures. ACM Trans. Embed. Comput. Syst. 13 (4) (2014)
Yu-Hsin Tsai, I-Wei Wu, I-Chun Liu, Jean Jyh-Jiun Shann
Improving performance of JNA by using LLVM JIT compiler. ICIS (2013)
Jhin-Bin Jiang, Kuen-Cheng Chiang, Jean Jyh-Jiun Shann
A predicate-aware modulo scheduling for improving resource efficiency of coarse grained reconfigurable architectures. SIES (2012)
Kuen-Cheng Chiang, Ming-Feng Wu, Jean Jyh-Jiun Shann
Modification and implementation of an edge-based fast intra prediction mode decision algorithm for H.264/AVC high resolution real-time systems. J. Vis. Commun. Image Represent. 23 (2) (2012)
I-Wei Wu, Chung-Ping Chung, Jean Jyh-Jiun Shann
Area-Efficient Instruction Set Extension Exploration with Hardware Design Space Exploration. J. Inf. Sci. Eng. 27 (5) (2011)
Hui-Shan Wang, I-Wei Wu, Jean Jyh-Jiun Shann, Chung-Ping Chung
Reconfigurable custom functional unit generation and exploitation in multiple-issue processors. SASP (2010)
Hsiu-ching Hsieh, Chih-Chieh Hsiao, Hui-Chin Yang, Chung-Ping Chung, Jean Jyh-Jiun Shann
Methods for Precise False-Overlap Detection in Tile-Based Rendering. CSE (2) (2009)
Jyh-Shian Wang, I-Wei Wu, Yu-Sheng Chen, Jean Jyh-Jiun Shann, Wei-Chung Hsu
Reducing Code Size by Graph Coloring Register Allocation and Assignment Algorithm for Mixed-Width ISA Processor. CSE (2) (2009)
I-Wei Wu, Zhiyuan Chen, Jean Jyh-Jiun Shann, Chung-Ping Chung
Instruction Set Extension Exploration in Multiple-Issue Architecture. DATE (2008)
Po-Chun Chang, I-Wei Wu, Jean Jyh-Jiun Shann, Chung-Ping Chung
ETAHM: an energy-aware task allocation algorithm for heterogeneous multiprocessor. DAC (2008)
I-Wei Wu, Shih-Chia Huang, Chung-Ping Chung, Jean Jyh-Jiun Shann
Instruction Set Extension Generation with Considering Physical Constraints. HiPEAC (2007)
Cher-Sheng Cheng, Jean Jyh-Jiun Shann, Chung-Ping Chung
Unique-order interpolative coding for fast querying and space-efficient indexing in information retrieval systems. Inf. Process. Manag. 42 (2) (2006)
Kuen-Cheng Chiang, Zhi-Wei Chen, Jean Jyh-Jiun Shann
Design and implementation of a reconfigurable hardware for secure embedded systems. AsiaCCS (2006)
Cher-Sheng Cheng, Chung-Ping Chung, Jean Jyh-Jiun Shann
Fast query evaluation through document identifier assignment for inverted file-based information retrieval systems. Inf. Process. Manag. 42 (3) (2006)
Wei-Hao Chiao, Tsung-Hsi Weng, Jean Jyh-Jiun Shann, Chung-Ping Chung, Jimmy Lu
Low-Power Data Address Bus Encoding Method. CDES (2005)
Yau-Chong Hu, Wei-Hau Chiao, Jean Jyh-Jiun Shann, Chung-Ping Chung, Wen-Feng Chen
Low-Power Branch Prediction. CDES (2005)
Cher-Sheng Cheng, Jean Jyh-Jiun Shann, Chung-Ping Chung
A Unique-Order Interpolative Code for Fast Querying and Space-Efficient Indexing in Information Retrieval Systems. ITCC (2) (2004)
Lee-Ren Ton, Lung-Chung Chang, Jean Jyh-Jiun Shann, Chung-Ping Chung
A software/hardware cooperated stack operations folding model for Java processors. J. Syst. Softw. 72 (3) (2004)
Kelvin Lin, Jean Jyh-Jiun Shann, Chung-Ping Chung
Code compression by register operand dependency. J. Syst. Softw. 72 (3) (2004)
Wann-Yun Shieh, Tien-Fu Chen, Jean Jyh-Jiun Shann, Chung-Ping Chung
Inverted file compression through document identifier reassignment. Inf. Process. Manag. 39 (1) (2003)
Kelvin Lin, Chung-Ping Chung, Jean Jyh-Jiun Shann
Compressing MIPS code by multiple operand dependencies. ACM Trans. Embed. Comput. Syst. 2 (4) (2003)
Wann-Yun Shieh, Jean Jyh-Jiun Shann, Chung-Ping Chung
An Inverted File Cache for Fast Information Retrieval. J. Inf. Sci. Eng. 19 (4) (2003)
Kelvin Lin, Jean Jyh-Jiun Shann, Chung-Ping Chung
Code Compression by Register Operand Dependency. Interaction between Compilers and Computer Architectures (2002)
Lee-Ren Ton, Lung-Chung Chang, Jean Jyh-Jiun Shann, Chung-Ping Chung
Design of an optimal folding mechanism for Java processors. Microprocess. Microsystems 26 (8) (2002)
R.-Ming Shiu, Hui-Yue Hwang, Jean Jyh-Jiun Shann
Aggressive Schduling for Memory Accesses of CISC Superscalar Microprocessors. J. Inf. Sci. Eng. 17 (5) (2001)
S.-K. Cheng, R.-Ming Shiu, Jean Jyh-Jiun Shann
Decoding Unit with High Issue Rate for X86 Superscalar Microprocessors. ICPADS (1998)
Hui-Yue Hwang, R.-Ming Shiu, Jean Jyh-Jiun Shann
An X86 Load/Store Unit with Aggressive Scheduling of Load/Store Operations. ICPADS (1998)
Hsin-Chia Fu, Jean Jyh-Jiun Shann
A Fuzzy Neural Network for Knowledge Learning. Int. J. Neural Syst. 5 (1) (1994)