Yu-Liang Chou

Publication Activity (10 Years)

Years Active: 2008-2022
Publications (10 Years): 5

Top Topics

Predictive Model

Energy Efficiency

Algorithmic Solutions

Top Venues

Decis. Support Syst.

Comput. Electr. Eng.

Publications

Yu-Liang Chou, Catarina Moreira, Peter Bruza, Chun Ouyang, Joaquim A. Jorge
Counterfactuals and causability in explainable artificial intelligence: Theory, algorithms, and applications. Inf. Fusion 81 (2022)
Yu-Liang Chou, Chihcheng Hsieh, Catarina Moreira, Chun Ouyang, Joaquim A. Jorge, João Madeiras Pereira
Benchmark Evaluation of Counterfactual Algorithms for XAI: From a White Box to a Black Box. CoRR (2022)
Yu-Liang Chou, Catarina Moreira, Peter Bruza, Chun Ouyang, Joaquim A. Jorge
Counterfactuals and Causability in Explainable Artificial Intelligence: Theory, Algorithms, and Applications. CoRR (2021)
Catarina Moreira, Yu-Liang Chou, Mythreyi Velmurugan, Chun Ouyang, Renuka Sindhgatta, Peter Bruza
LINDA-BN: An interpretable probabilistic approach for demystifying black-box predictive models. Decis. Support Syst. 150 (2021)
Catarina Moreira, Yu-Liang Chou, Mythreyi Velmurugan, Chun Ouyang, Renuka Sindhgatta, Peter Bruza
An Interpretable Probabilistic Approach for Demystifying Black-box Predictive Models. CoRR (2020)
Yu-Liang Chou, Shaoshan Liu, Eui-Young Chung, Jean-Luc Gaudiot
An Energy and Performance Efficient DVFS Scheme for Irregular Parallel Divide-and-Conquer Algorithms on the Intel SCC. IEEE Comput. Archit. Lett. 13 (1) (2014)
Jih-Ching Chiu, Kai-Ming Yang, Yu-Liang Chou, Chih-Kang Wu
A relation-exchanging buffering mechanism for instruction and data streaming. Comput. Electr. Eng. 39 (4) (2013)
Jih-Ching Chiu, Kai-Ming Yang, Yu-Liang Chou
A hyperscalar dual-core architecture for embedded systems. Microprocess. Microsystems 37 (8-B) (2013)
Jie Tang, Chen Liu, Yu-Liang Chou, Shaoshan Liu
OCP: Offload Co-Processor for energy efficiency in embedded mobile systems. ASAP (2013)
Jih-Ching Chiu, Yu-Liang Chou, Po-Kai Chen, Ding-Siang Su
A Unitable Computing Architecture for Chip Multiprocessors. Comput. J. 54 (12) (2011)
Jih-Ching Chiu, Yu-Liang Chou, Tseng-Kuei Lin
The Basic Block Reassembling Instruction Stream Buffer with LWBTB for X86 ISA. J. Inf. Sci. Eng. 26 (4) (2010)
Jih-Ching Chiu, Yu-Liang Chou
A multi-streaming SIMD multimedia computing engine. Microprocess. Microsystems 34 (7-8) (2010)
Jih-Ching Chiu, Yu-Liang Chou, Po-Kai Chen
Hyperscalar: A Novel Dynamically Reconfigurable Multi-core Architecture. ICPP (2010)
Jih-Ching Chiu, Yu-Liang Chou, Ding-Siang Su
A hyperscalar multi-core architecture. Conf. Computing Frontiers (2010)
Jih-Ching Chiu, Yu-Liang Chou, Hua-Yi Tzeng
A multi-streaming SIMD architecture for multimedia applications. Conf. Computing Frontiers (2009)
Jih-Ching Chiu, Kai-Ming Yang, Yu-Liang Chou
Design of a novel SIMD architecture by fusing operations and registers. ICS (2009)
Jih-Ching Chiu, Yu-Liang Chou, Ta-Li Yeh, Tseng-Kuei Lin
Designs of the basic block reassembling Instruction Stream Buffer for X86 ISA. ACSAC (2008)
Jih-Ching Chiu, Yu-Liang Chou, Ren-Bang Lin
The Multi-context Reconfigurable Processing Unit for Fine-grain Computing. J. Inf. Sci. Eng. 24 (3) (2008)