Chih-Da Chien

Publication Activity (10 Years)

Years Active: 2002-2016
Publications (10 Years): 2

Top Topics

Latent Semantic Indexing

Top Venues

IEEE J. Solid State Circuits

Publications

Chi-Cheng Ju, Tsu-Ming Liu, Kun-Bin Lee, Yung-Chang Chang, Han-Liang Chou, Chih-Ming Wang, Tung-Hsing Wu, Hue-Min Lin, Yi-Hsin Huang, Chia-Yun Cheng, Ting-An Lin, Chun-Chia Chen, Yu-Kun Lin, Min-Hao Chiu, Wei-Cing Li, Sheng-Jen Wang, Yen-Chieh Lai, Ping Chao, Chih-Da Chien, Meng-Jye Hu, Peng-Hao Wang, Yen-Chao Huang, Shun-Hsiang Chuang, Lien-Fei Chen, Hsiu-Yi Lin, Ming-Long Wu, Che-Hong Chen
A 0.5 nJ/Pixel 4 K H.265/HEVC Codec LSI for Multi-Format Smartphone Applications. IEEE J. Solid State Circuits 51 (1) (2016)
Chi-Cheng Ju, Tsu-Ming Liu, Kun-Bin Lee, Yung-Chang Chang, Han-Liang Chou, Chih-Ming Wang, Tung-Hsing Wu, Hue-Min Lin, Yi-Hsin Huang, Chia-Yun Cheng, Ting-An Lin, Chun-Chia Chen, Yu-Kun Lin, Min-Hao Chiu, Wei-Cing Li, Sheng-Jen Wang, Yen-Chieh Lai, Ping Chao, Chih-Da Chien, Meng-Jye Hu, Peng-Hao Wang, Fu-Chun Yeh, Yen-Chao Huang, Shun-Hsiang Chuang, Lien-Fei Chen, Hsiu-Yi Lin, Ming-Long Wu, Che-Hong Chen, Ryan Chen, H. Y. Hsu, Kevin Jou
18.6 A 0.5nJ/pixel 4K H.265/HEVC codec LSI for multi-format smartphone applications. ISSCC (2015)
Cheng-An Chien, Chih-Da Chien, Jui-Chin Chu, Jiun-In Guo, Ching-Hwa Cheng
A Multi-standard Video Decoder for High Definition Video Applications. ISCAS (2009)
Chih-Da Chien, Cheng-An Chien, Jui-Chin Chu, Jiun-In Guo, Ching-Hwa Cheng
A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications. ACM Trans. Design Autom. Electr. Syst. 14 (1) (2009)
Chih-Da Chien, Chih-Wei Wang, Chiun-Chau Lin, Tien-Wei Hsieh, Yuan-Hwa Chu, Jiun-In Guo
A Low Latency Memory Controller for Video Coding Systems. ICME (2007)
Chih-Da Chien, Chien-Chang Lin, Yi-Hung Shih, He-Chun Chen, Chia-Jui Huang, Cheng-Yen Yu, Chih-Liang Chen, Ching-Hwa Cheng, Jiun-In Guo
A 252kgate/71mW Multi-Standard Multi-Channel Video Decoder for High Definition Video Applications. ISSCC (2007)
Guo-An Jian, Chih-Da Chien, Jiun-In Guo
A Memory-Based Hardware Accelerator for Real-Time MPEG-4 Audio Coding and Reverberation. ISCAS (2007)
Chih-Da Chien, Keng-Po Lu, Yi-Hung Shih, Jiun-In Guo
A high performance CAVLC encoder design for MPEG-4 AVC/H.264 video coding applications. ISCAS (2006)
Chih-Da Chien, Ho-Chun Chen, Lin-Chieh Huang, Jiun-In Guo
A low-power motion compensation IP core design for MPEG-1/2/4 video decoding. ISCAS (5) (2005)
Chih-Da Chien, Chien-Chang Lin, Jiun-In Guo, Tien-Fu Chen
A power-aware IP core generator for the one-dimensional discrete Fourier transform. ISCAS (3) (2004)
Tai-Lun Chang, Ying-Ming Tsai, Chih-Da Chien, Chien-Chang Lin, Jiun-In Guo
A high-performance MPEG4 bitstream processing core. ICME (2004)
Jiun-In Guo, Chih-Da Chien, Chien-Chang Lin
A parameterized low power design for the variable-length discrete Fourier transform using dynamic pipelining. ISCAS (5) (2003)
Jiun-In Guo, Chien-Chang Lin, Chih-Da Chien
A Low-Power Parameterized Hardware Design for the One-Dimensional Discrete Fourier Transform of Variable Lengths. J. Circuits Syst. Comput. 11 (4) (2002)